---------- Begin Simulation Statistics ----------
simSeconds 0.000003 # Number of seconds simulated (Second)
simTicks 2811852 # Number of ticks simulated (Tick)
finalTick 8702955 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.04 # Real time elapsed on the host (Second)
hostTickRate 67412721 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3391440 # Number of bytes of host memory used (Byte)
simInsts 3004 # Number of instructions simulated (Count)
simOps 5722 # Number of ops (including micro ops) simulated (Count)
hostInstRate 71821 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 136769 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 413 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 413 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 413 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 413 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::processor.switch.core.data 58 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::total 58 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::processor.switch.core.data 58 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::total 58 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::processor.switch.core.data 3096900 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::total 3096900 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::processor.switch.core.data 3096900 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::total 3096900 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 471 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 471 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 471 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 471 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissRate::processor.switch.core.data 0.123142 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMissRate::total 0.123142 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::processor.switch.core.data 0.123142 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::total 0.123142 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::processor.switch.core.data 53394.827586 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::total 53394.827586 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::processor.switch.core.data 53394.827586 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::total 53394.827586 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.demandMshrHits::processor.switch.core.data 20 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::total 20 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::processor.switch.core.data 20 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::total 20 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::processor.switch.core.data 38 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::total 38 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::processor.switch.core.data 38 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::total 45 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::processor.switch.core.data 2244420 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::total 2244420 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 725930 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::processor.switch.core.data 2244420 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::total 2970350 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::processor.switch.core.data 0.080679 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::total 0.080679 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::processor.switch.core.data 0.080679 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::total 0.095541 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::processor.switch.core.data 59063.684211 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::total 59063.684211 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 103704.285714 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::processor.switch.core.data 59063.684211 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::total 66007.777778 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::total 7 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 725930 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::total 725930 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 103704.285714 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::total 103704.285714 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 245 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 245 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::processor.switch.core.data 41 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::total 41 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::processor.switch.core.data 1888110 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::total 1888110 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 286 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 286 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::processor.switch.core.data 0.143357 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::total 0.143357 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::processor.switch.core.data 46051.463415 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::total 46051.463415 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::processor.switch.core.data 20 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::total 20 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::processor.switch.core.data 21 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::total 21 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::processor.switch.core.data 1041291 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::total 1041291 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::processor.switch.core.data 0.073427 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::total 0.073427 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::processor.switch.core.data 49585.285714 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::total 49585.285714 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 168 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 168 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::processor.switch.core.data 17 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::total 17 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::processor.switch.core.data 1208790 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::total 1208790 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 185 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 185 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::processor.switch.core.data 0.091892 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::total 0.091892 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::processor.switch.core.data 71105.294118 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::total 71105.294118 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::processor.switch.core.data 17 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::total 17 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::processor.switch.core.data 1203129 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::total 1203129 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::processor.switch.core.data 0.091892 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::total 0.091892 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::processor.switch.core.data 70772.294118 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::total 70772.294118 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 38 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 16 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 2 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy 0.125000 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage 0.050000 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 4 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 5 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 9 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 16 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 108.771800 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 18.831717 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 88.940083 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.036781 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.001953 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.173711 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 0.212445 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1022 25 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 109 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1022::0 25 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::0 109 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1022 0.048828 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 0.212891 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3813 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3813 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 220 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 220 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 220 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 220 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::processor.switch.core.inst 79 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::total 79 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::processor.switch.core.inst 79 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::total 79 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::processor.switch.core.inst 4399929 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::total 4399929 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::processor.switch.core.inst 4399929 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::total 4399929 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 299 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 299 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 299 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 299 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissRate::processor.switch.core.inst 0.264214 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMissRate::total 0.264214 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::processor.switch.core.inst 0.264214 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::total 0.264214 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::processor.switch.core.inst 55695.303797 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::total 55695.303797 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::processor.switch.core.inst 55695.303797 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::total 55695.303797 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.demandMshrHits::processor.switch.core.inst 20 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::total 20 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::processor.switch.core.inst 20 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::total 20 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::processor.switch.core.inst 59 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::total 59 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::processor.switch.core.inst 59 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::total 59 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::processor.switch.core.inst 3594402 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::total 3594402 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::processor.switch.core.inst 3594402 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::total 3594402 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::processor.switch.core.inst 0.197324 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::total 0.197324 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::processor.switch.core.inst 0.197324 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::total 0.197324 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::processor.switch.core.inst 60922.067797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::total 60922.067797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::processor.switch.core.inst 60922.067797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::total 60922.067797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 220 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 220 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::processor.switch.core.inst 79 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::total 79 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::processor.switch.core.inst 4399929 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::total 4399929 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 299 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 299 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::processor.switch.core.inst 0.264214 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::total 0.264214 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::processor.switch.core.inst 55695.303797 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::total 55695.303797 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::processor.switch.core.inst 20 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::total 20 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::processor.switch.core.inst 59 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::total 59 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::processor.switch.core.inst 3594402 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::total 3594402 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::processor.switch.core.inst 0.197324 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::total 0.197324 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::processor.switch.core.inst 60922.067797 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::total 60922.067797 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 59 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 155.668177 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 154.668177 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.001953 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.302086 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.304039 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 185 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::0 185 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 0.361328 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 2452 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 2452 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.demandMisses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.switch.core.inst 59 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.switch.core.data 38 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::total 104 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.switch.core.inst 59 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.switch.core.data 38 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::total 104 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.demandMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 721275 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.switch.core.inst 3553776 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.switch.core.data 2217780 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::total 6492831 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 721275 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.switch.core.inst 3553776 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.switch.core.data 2217780 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::total 6492831 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandAccesses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.switch.core.inst 59 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.switch.core.data 38 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::total 104 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.switch.core.inst 59 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.switch.core.data 38 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::total 104 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandMissRate::cache_hierarchy.l1d-cache-0.prefetcher 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.switch.core.inst 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.switch.core.data 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::total 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::cache_hierarchy.l1d-cache-0.prefetcher 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.switch.core.inst 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.switch.core.data 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::total 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 103039.285714 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.switch.core.inst 60233.491525 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.switch.core.data 58362.631579 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::total 62431.067308 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 103039.285714 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.switch.core.inst 60233.491525 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.switch.core.data 58362.631579 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::total 62431.067308 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.demandMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 3 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::total 3 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 3 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::total 3 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 4 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.switch.core.inst 59 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.switch.core.data 38 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::total 101 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 4 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l2-cache-0.prefetcher 5 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.switch.core.inst 59 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.switch.core.data 38 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::total 106 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 604062 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.switch.core.inst 3533796 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.switch.core.data 2205126 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::total 6342984 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 604062 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 224100 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.switch.core.inst 3533796 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.switch.core.data 2205126 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::total 6567084 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.571429 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.switch.core.inst 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.switch.core.data 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::total 0.971154 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.571429 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.switch.core.inst 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.switch.core.data 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::total 1.019231 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 151015.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.switch.core.inst 59894.847458 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.switch.core.data 58029.631579 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::total 62801.821782 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 151015.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 44820 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.switch.core.inst 59894.847458 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.switch.core.data 58029.631579 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::total 61953.622642 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l2-cache-0.prefetcher 5 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::total 5 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 224100 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::total 224100 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 44820 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::total 44820 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::processor.switch.core.data 17 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::total 17 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::processor.switch.core.data 1191807 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::total 1191807 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::processor.switch.core.data 17 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::total 17 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::processor.switch.core.data 1 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::total 1 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::processor.switch.core.data 70106.294118 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::total 70106.294118 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::processor.switch.core.data 17 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::total 17 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::processor.switch.core.data 1186146 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::total 1186146 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::processor.switch.core.data 1 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::total 1 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::processor.switch.core.data 69773.294118 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::total 69773.294118 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.switch.core.inst 59 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.switch.core.data 21 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::total 87 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::cache_hierarchy.l1d-cache-0.prefetcher 721275 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.switch.core.inst 3553776 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.switch.core.data 1025973 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::total 5301024 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::cache_hierarchy.l1d-cache-0.prefetcher 7 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.switch.core.inst 59 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.switch.core.data 21 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::total 87 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::cache_hierarchy.l1d-cache-0.prefetcher 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.switch.core.inst 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.switch.core.data 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::total 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 103039.285714 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.switch.core.inst 60233.491525 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.switch.core.data 48855.857143 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::total 60931.310345 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::cache_hierarchy.l1d-cache-0.prefetcher 3 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::total 3 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 4 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.switch.core.inst 59 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.switch.core.data 21 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::total 84 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 604062 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.switch.core.inst 3533796 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.switch.core.data 1018980 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::total 5156838 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.571429 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.switch.core.inst 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.switch.core.data 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::total 0.965517 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 151015.500000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.switch.core.inst 59894.847458 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.switch.core.data 48522.857143 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::total 61390.928571 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 101 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 7 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy 0 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 2 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 2 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 8 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 1 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 268.489125 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 13.198249 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 9.659049 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 154.682507 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 88.949320 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.003222 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.002358 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.037764 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.021716 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.065549 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 294 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::0 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::0 294 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.071777 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 1771 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 1771 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.transDist::ReadResp 88 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::HardPFReq 6 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExReq 17 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExResp 17 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadSharedReq 87 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 119 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 90 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount::total 209 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 3840 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 2880 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize::total 6720 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.snoops 6 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 110 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 110 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 110 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.reqLayer0.occupancy 34962 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer0.occupancy 59940 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer1.occupancy 44955 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 104 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.transDist::ReadResp 90 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 17 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 17 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 90 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 106 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 108 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::total 214 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 214 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 3392 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 3456 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::total 6848 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 6848 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 107 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 107 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 107 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 18313 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 18644 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 87762 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 107 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 2.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 3.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch.core.inst::samples 27.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch.core.data::samples 21.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000736348 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 108 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 53 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 53 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 1.52 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 53 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 35 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 13 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 3392 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 1206322381.12105465 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 2798199 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 52796.21 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 192 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch.core.inst 1728 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch.core.data 1344 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 45521599.287586972117 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 68282398.931380450726 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch.core.inst 614541590.382424116135 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch.core.data 477976792.519663155079 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 2 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 3 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch.core.inst 27 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch.core.data 21 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 64660 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 67479 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch.core.inst 1267943 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch.core.data 445797 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 32330.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 22493.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch.core.inst 46960.85 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch.core.data 21228.43 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 192 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch.core.inst 1728 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch.core.data 1344 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 3392 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.switch.core.inst 1728 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 1728 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 2 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 3 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch.core.inst 27 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch.core.data 21 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 53 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 45521599 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 68282399 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch.core.inst 614541590 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch.core.data 477976793 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 1206322381 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.switch.core.inst 614541590 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 614541590 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 45521599 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 68282399 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch.core.inst 614541590 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch.core.data 477976793 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 1206322381 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 53 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 6 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 12 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 9 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 14 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 918803 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 176596 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 1845879 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 17335.91 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 34827.91 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 43 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 81.13 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 14 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 241.179719 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 317.387135 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 4 28.57% 28.57% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 2 14.29% 42.86% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::256-383 2 14.29% 57.14% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::384-511 1 7.14% 64.29% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::512-639 1 7.14% 71.43% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::640-767 2 14.29% 85.71% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::768-895 1 7.14% 92.86% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 1 7.14% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 14 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 3392 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 1206.322381 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 6.28 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 6.28 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 81.13 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 35865.648000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 49552.171200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 441607.286400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 675855.549600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 4065241.252800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 9244.300800 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 5277366.208800 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 1876.829296 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 350000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 8276365 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 675855.549600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 159112.329600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 807788.755200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 1642756.634400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 584.225853 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 8351290 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 350000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 2.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 2.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch.core.inst::samples 33.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch.core.data::samples 17.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000772650 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 110 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 54 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 54 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.62 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 54 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 37 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 14 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 3456 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 1229083180.76484823 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 2795535 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 51769.17 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch.core.inst 2112 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch.core.data 1088 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 45521599.287586972117 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 45521599.287586972117 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch.core.inst 751106388.245185017586 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch.core.data 386933593.944489240646 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 2 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 2 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch.core.inst 33 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch.core.data 17 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 430816 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 36652 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch.core.inst 636217 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch.core.data 725682 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 215408.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 18326.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch.core.inst 19279.30 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch.core.data 42687.18 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch.core.inst 2112 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch.core.data 1088 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 3456 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.switch.core.inst 2112 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 2112 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 2 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 2 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch.core.inst 33 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch.core.data 17 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 54 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 45521599 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 45521599 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch.core.inst 751106388 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch.core.data 386933594 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 1229083181 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.switch.core.inst 751106388 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 751106388 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 45521599 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 45521599 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch.core.inst 751106388 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch.core.data 386933594 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 1229083181 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 54 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 5 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 14 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 9 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 13 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 884799 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 179928 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 1829367 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 16385.17 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 33877.17 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 47 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 87.04 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 13 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 497.230769 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 384.424870 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 331.684125 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 4 30.77% 30.77% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 1 7.69% 38.46% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::384-511 1 7.69% 46.15% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::512-639 3 23.08% 69.23% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::768-895 2 15.38% 84.62% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 2 15.38% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 13 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 3456 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 1229.083181 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 6.40 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 6.40 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 87.04 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 31187.520000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 44046.374400 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 444350.188800 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 675855.549600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 4098324.014400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 9244.300800 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 5303007.948000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 1885.948460 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 350000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 8346961 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 675855.549600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 159112.329600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 807788.755200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 1642756.634400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 584.225853 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 8351290 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 350000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 8701290 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 8444 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 8.427146 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 0.118664 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 3269 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2926 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsIssued 6 # Number of squashed instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 1511 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 2133 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 5305 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 0.551555 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.592790 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 4549 85.75% 85.75% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 135 2.54% 88.29% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 133 2.51% 90.80% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 94 1.77% 92.57% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 110 2.07% 94.65% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 84 1.58% 96.23% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 76 1.43% 97.66% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 65 1.23% 98.89% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 59 1.11% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 5305 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 44 88.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 88.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 1 2.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 0.00% 90.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 4 8.00% 98.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 98.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 1 2.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 38 1.30% 1.30% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 2236 76.42% 77.72% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 1 0.03% 77.75% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 77.75% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 9 0.31% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 78.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 39 1.33% 79.39% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 79.39% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 6 0.21% 79.60% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 9 0.31% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 79.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 320 10.94% 90.84% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 230 7.86% 98.70% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 20 0.68% 99.38% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 18 0.62% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2926 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 0.346518 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 50 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.017088 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 11003 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 4609 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2711 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 210 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 172 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 97 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2832 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 106 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 81 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.timesIdled 31 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.switch.core.idleCycles 3139 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.switch.core.MemDepUnit__0.insertedLoads 380 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 280 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 1 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 5 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 48 10.79% 10.79% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 35 7.87% 18.65% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 7 1.57% 20.22% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 306 68.76% 88.99% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 31 6.97% 95.96% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 95.96% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 18 4.04% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 445 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 30 11.95% 11.95% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 20 7.97% 19.92% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 4 1.59% 21.51% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 171 68.13% 89.64% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 17 6.77% 96.41% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 96.41% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 9 3.59% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 251 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 16 23.53% 23.53% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 4 5.88% 29.41% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 34 50.00% 79.41% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 10 14.71% 94.12% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 94.12% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 4 5.88% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 68 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 19 9.95% 9.95% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 15 7.85% 17.80% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 3 1.57% 19.37% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 132 69.11% 88.48% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 15 7.85% 96.34% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 96.34% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 7 3.66% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 191 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 8 15.69% 15.69% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 3 5.88% 21.57% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 29 56.86% 78.43% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 7 13.73% 92.16% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 92.16% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 4 7.84% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 51 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 298 66.97% 66.97% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 101 22.70% 89.66% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 46 10.34% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 445 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 64 94.12% 94.12% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 4 5.88% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 68 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 306 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 68 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 36 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 64 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 4 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 445 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 56 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 121 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 0.271910 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 50 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 25 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 25 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 48 10.79% 10.79% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 35 7.87% 18.65% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 7 1.57% 20.22% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 306 68.76% 88.99% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 31 6.97% 95.96% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 95.96% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 18 4.04% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 445 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 48 14.81% 14.81% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 20 6.17% 20.99% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 7 2.16% 23.15% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 215 66.36% 89.51% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 16 4.94% 94.44% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 0.00% 94.44% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 18 5.56% 100.00% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 324 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 16 28.57% 28.57% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 0.00% 28.57% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 30 53.57% 82.14% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 10 17.86% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 56 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 16 28.57% 28.57% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 28.57% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 30 53.57% 82.14% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 10 17.86% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 56 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 25 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 25 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 8 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 33 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 72 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 72 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 54 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 19 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 19 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 1511 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 42 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 5084 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 0.350708 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 1.378975 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 4632 91.11% 91.11% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 106 2.08% 93.19% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 73 1.44% 94.63% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 77 1.51% 96.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 47 0.92% 97.07% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 13 0.26% 97.32% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 17 0.33% 97.66% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 7 0.14% 97.80% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 112 2.20% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 5084 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 18 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 22 1.23% 1.23% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1363 76.44% 77.68% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 1 0.06% 77.73% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 77.73% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 5 0.28% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 78.01% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 12 0.67% 78.69% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 78.69% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 2 0.11% 78.80% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 5 0.28% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 79.08% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 183 10.26% 89.34% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 167 9.37% 98.71% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 6 0.34% 99.05% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 17 0.95% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1783 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 112 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1002 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1783 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1002 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1783 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 8.427146 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 0.118664 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 373 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 50 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1738 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 189 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 184 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 22 1.23% 1.23% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1363 76.44% 77.68% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 1 0.06% 77.73% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 77.73% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 5 0.28% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 78.01% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 12 0.67% 78.69% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 78.69% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 2 0.11% 78.80% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 5 0.28% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 79.08% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 183 10.26% 89.34% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 167 9.37% 98.71% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 6 0.34% 99.05% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 17 0.95% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1783 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 193 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 163 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsIndirectControl 30 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 133 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 60 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCall 18 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsReturn 19 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 4113 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 593 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 509 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 47 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 43 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 121 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.branchMispred 26 # Number of times decode detected a branch misprediction (Count)
board.processor.switch.core.decode.decodedInsts 3633 # Number of instructions handled by decode (Count)
board.processor.switch.core.decode.squashedInsts 155 # Number of squashed instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2845 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 273 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 323 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 238 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 0.336926 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 1159 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 814 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegReads 129 # Number of times the floating registers were read (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 74 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 3061 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 2017 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 561 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1244 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 147 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 1119 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 138 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 299 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.icacheSquashes 38 # Number of outstanding Icache misses that were squashed (Count)
board.processor.switch.core.fetch.nisnDist::samples 5305 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 0.789444 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 2.263797 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 4655 87.75% 87.75% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 39 0.74% 88.48% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 21 0.40% 88.88% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 68 1.28% 90.16% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 13 0.25% 90.41% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 36 0.68% 91.08% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 34 0.64% 91.72% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 45 0.85% 92.57% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 394 7.43% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 5305 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 2244 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 0.265751 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 445 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.052700 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.icacheStallCycles 4117 # ICache total stall cycles (Cycle)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 43 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 256 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 2 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 3269 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 8 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 380 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 280 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 1 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 1 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 4 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 42 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 46 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2823 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2808 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1877 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 2951 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 0.332544 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.636056 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 39 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 194 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 1 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 99 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 186 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 15.107527 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 41.725736 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 169 90.86% 90.86% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::40-49 1 0.54% 91.40% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::120-129 1 0.54% 91.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::130-139 7 3.76% 95.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::140-149 3 1.61% 97.31% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::150-159 1 0.54% 97.85% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::160-169 1 0.54% 98.39% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::180-189 3 1.61% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 182 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 186 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 326 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 238 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 4 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 299 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 6 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 8702955 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 43 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 4159 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 561 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 500 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 42 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 3493 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full (Count)
board.processor.switch.core.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.SQFullEvents 1 # Number of times rename has blocked due to SQ full (Count)
board.processor.switch.core.rename.renamedOperands 5741 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 11520 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 3999 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.fpLookups 157 # Number of floating rename lookups (Count)
board.processor.switch.core.rename.committedMaps 2762 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 2969 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 138 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 8266 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 6787 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1002 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1783 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 314685 # Number of ticks simulated (Tick)
finalTick 148798719 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 8997941 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 186005 # Number of instructions simulated (Count)
simOps 363818 # Number of ops (including micro ops) simulated (Count)
hostInstRate 5302158 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 10367548 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 489 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 489 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 489 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 489 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 489 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 489 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 489 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 489 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 267 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 267 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 267 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 267 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::1 423 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 89 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3912 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3912 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 105 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 105 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 105 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 105 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 105 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 105 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 105 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 105 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 105 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 105 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 105 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 105 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::1 309 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 203 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 840 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 840 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::1 764 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 1598 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 148478.584800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 148478.584800 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.832419 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 849483 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 849483 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 148478.584800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 148478.584800 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.832419 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 849483 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 849483 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 945 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.945000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.058201 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2578 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2401 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsIssued 2 # Number of squashed instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 576 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 1090 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 945 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.540741 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.851672 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 132 13.97% 13.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 182 19.26% 33.23% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 160 16.93% 50.16% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 230 24.34% 74.50% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 114 12.06% 86.56% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 69 7.30% 93.86% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 12 1.27% 95.13% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 32 3.39% 98.52% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 14 1.48% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 945 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 2 66.67% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 66.67% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 1 33.33% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 8 0.33% 0.33% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1427 59.43% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 59.77% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 712 29.65% 89.42% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 254 10.58% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2401 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.540741 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 3 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.001249 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 5752 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 3157 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2320 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2396 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 60 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 753 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 277 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 485 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 132 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 2 0.82% 0.82% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 2 0.82% 1.64% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 2 0.82% 2.46% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 193 79.10% 81.56% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 39 15.98% 97.54% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 97.54% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 6 2.46% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 244 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 2 1.53% 1.53% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 2 1.53% 3.05% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 2 1.53% 4.58% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 81 61.83% 66.41% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 38 29.01% 95.42% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 95.42% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 6 4.58% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 131 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 12 92.31% 92.31% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 1 7.69% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 13 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 99.12% 99.12% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 1 0.88% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 113 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 12 92.31% 92.31% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 1 7.69% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 13 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 60 24.59% 24.59% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 182 74.59% 99.18% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 2 0.82% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 244 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 12 92.31% 92.31% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 1 7.69% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 13 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 193 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 142 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 13 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 1 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 12 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 1 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 244 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 12 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 227 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 0.930328 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 2 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 8 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 8 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 2 0.82% 0.82% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 2 0.82% 1.64% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 2 0.82% 2.46% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 193 79.10% 81.56% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 39 15.98% 97.54% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 97.54% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 6 2.46% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 244 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 2 11.76% 11.76% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 0.00% 11.76% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 2 11.76% 23.53% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 6 35.29% 58.82% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 1 5.88% 64.71% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 0.00% 64.71% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 6 35.29% 100.00% # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 17 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 11 91.67% 91.67% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 1 8.33% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 12 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 11 91.67% 91.67% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 1 8.33% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 12 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 8 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 8 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 8 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 6 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 6 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 6 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 576 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 12 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 861 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.329849 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.644064 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 194 22.53% 22.53% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 326 37.86% 60.39% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 117 13.59% 73.98% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 4 0.46% 74.45% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 6 0.70% 75.15% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 99 11.50% 86.64% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 86.64% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 5 0.58% 87.22% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 110 12.78% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 861 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1120 55.83% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 664 33.10% 88.93% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.07% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 2006 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 110 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 2006 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 2006 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.945000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.058201 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 886 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 2006 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 664 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1120 55.83% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 664 33.10% 88.93% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.07% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 2006 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 114 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 114 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 134 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 430 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 125 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 241 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 15 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 174 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.branchMispred 1 # Number of times decode detected a branch misprediction (Count)
board.processor.switch.core.decode.decodedInsts 2815 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2341 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 138 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 704 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 250 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.477249 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 590 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 922 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2634 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1830 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 954 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1268 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 184 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 920 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 32 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 105 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.nisnDist::samples 945 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 3.191534 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.371480 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 421 44.55% 44.55% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 10 1.06% 45.61% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 100 10.58% 56.19% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 1 0.11% 56.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 51 5.40% 61.69% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 38 4.02% 65.71% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 90 9.52% 75.24% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 3 0.32% 75.56% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 231 24.44% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 945 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1386 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.466667 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 244 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.258201 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.icacheStallCycles 9 # ICache total stall cycles (Cycle)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 15 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 69 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2578 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 753 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 277 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 5 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 12 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 13 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2341 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2320 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1836 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1967 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.455026 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933401 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 437 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 90 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 5 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 55 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 665 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2.030075 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 0.170923 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 665 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 665 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 704 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 250 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 2 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 105 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 140095764 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 15 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 173 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 67 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 321 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 369 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2740 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.LQFullEvents 337 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 4984 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 9423 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 3122 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3897 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 1112 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 888 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 3333 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 5246 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 2006 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 296216154 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7802805 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 369007 # Number of instructions simulated (Count)
simOps 729962 # Number of ops (including micro ops) simulated (Count)
hostInstRate 11092284 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 21934613 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 842823 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 842823 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 842823 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 842823 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 195 25.10% 25.10% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 165 21.24% 46.33% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 251 32.30% 78.64% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 110 14.16% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4773 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1998 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1998 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.571429 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1554 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.331356 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 443 57.01% 57.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 56 7.21% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 56 7.21% 78.64% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.64% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 166 21.36% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1000 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.287001 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1998 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1998 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1581 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1692 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.571429 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934397 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147417435 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 138 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2002 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 389 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3893 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7342 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2446 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 975 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 443573982 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7856349 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 552009 # Number of instructions simulated (Count)
simOps 1096106 # Number of ops (including micro ops) simulated (Count)
hostInstRate 16706789 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 33162073 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 590931810 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7829248 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 735011 # Number of instructions simulated (Count)
simOps 1462250 # Number of ops (including micro ops) simulated (Count)
hostInstRate 22168934 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 44075537 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 738292302 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7849300 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 918012 # Number of instructions simulated (Count)
simOps 1828398 # Number of ops (including micro ops) simulated (Count)
hostInstRate 27711897 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 55180263 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2003 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2001 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571979 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.209395 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.59% 46.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 249 32.01% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.80% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.20% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1112 55.57% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.33% 88.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2001 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571979 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4780 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2003 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2000 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2001 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 668 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 445 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 251 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2008 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2001 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.571979 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1555 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335124 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 445 57.20% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.07% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.07% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.47% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.284062 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2003 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 668 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2000 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2000 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1585 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1697 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570694 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934001 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2008 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3904 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7361 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2453 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3999 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 885651129 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.04 # Real time elapsed on the host (Second)
hostTickRate 6798954 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 1101013 # Number of instructions simulated (Count)
simOps 2194541 # Number of ops (including micro ops) simulated (Count)
hostInstRate 28848006 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 57481822 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 1033008957 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7853011 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 1284015 # Number of instructions simulated (Count)
simOps 2560685 # Number of ops (including micro ops) simulated (Count)
hostInstRate 38822489 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 77401838 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 453 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 59 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 324 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 188 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 990 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 1372 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 1180369449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.04 # Real time elapsed on the host (Second)
hostTickRate 6942147 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 1467016 # Number of instructions simulated (Count)
simOps 2926833 # Number of ops (including micro ops) simulated (Count)
hostInstRate 39154883 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 78078029 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2001 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2000 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.570694 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.207341 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.59% 46.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 249 32.01% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 112 14.40% 92.93% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 55 7.07% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1111 55.55% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.35% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2000 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.570694 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4779 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2001 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2000 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2000 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 667 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 251 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2008 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2001 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.571979 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1555 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.336667 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 445 57.20% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 56 7.20% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 54 6.94% 71.34% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.34% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 56 7.20% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.47% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1001 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.286632 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2001 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 667 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2000 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2000 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570694 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2008 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3903 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7362 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2454 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 975 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3999 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 1327727943 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7700167 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 1650017 # Number of instructions simulated (Count)
simOps 3292976 # Number of ops (including micro ops) simulated (Count)
hostInstRate 48877807 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 97459927 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 1475085771 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7761842 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 1833019 # Number of instructions simulated (Count)
simOps 3659120 # Number of ops (including micro ops) simulated (Count)
hostInstRate 54746401 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 109233984 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 1622446263 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7809314 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2016020 # Number of instructions simulated (Count)
simOps 4025268 # Number of ops (including micro ops) simulated (Count)
hostInstRate 60497539 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 120726651 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1999 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2000 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.570694 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.206275 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 167 21.47% 46.40% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 251 32.26% 78.66% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.93% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 55 7.07% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1111 55.55% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.35% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2000 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.570694 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4780 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1999 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2001 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2000 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 667 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 417 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2002 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.573265 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1556 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.560411 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.330693 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 446 57.33% 57.33% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.33% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.07% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.59% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.59% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.07% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 166 21.34% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 996 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.280206 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1999 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 667 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2001 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2001 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.571979 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 417 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 1998 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 389 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3885 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7326 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2442 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 962 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3991 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 1769804757 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7737701 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2199021 # Number of instructions simulated (Count)
simOps 4391411 # Number of ops (including micro ops) simulated (Count)
hostInstRate 65468487 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 130669533 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 1917162585 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7773035 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2382023 # Number of instructions simulated (Count)
simOps 4757555 # Number of ops (including micro ops) simulated (Count)
hostInstRate 71177404 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 142109893 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 2064523077 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7865744 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2565024 # Number of instructions simulated (Count)
simOps 5123703 # Number of ops (including micro ops) simulated (Count)
hostInstRate 77603364 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 154963193 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2005 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2002 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.573265 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210382 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 195 25.06% 25.06% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 165 21.21% 46.27% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 251 32.26% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.80% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.20% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1113 55.59% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.32% 88.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2002 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.573265 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4782 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2005 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2001 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2002 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 668 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 445 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 417 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2002 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.573265 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1556 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.330490 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.07% 57.07% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.07% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 56 7.20% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 56 7.20% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 166 21.34% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1000 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285347 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2005 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 668 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2001 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2001 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.571979 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 138 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 417 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2006 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 390 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3902 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7358 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2452 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 975 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4001 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 2211881904 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7803040 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2748025 # Number of instructions simulated (Count)
simOps 5489846 # Number of ops (including micro ops) simulated (Count)
hostInstRate 82458891 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 164652570 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 2359239732 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7647593 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 2931027 # Number of instructions simulated (Count)
simOps 5855990 # Number of ops (including micro ops) simulated (Count)
hostInstRate 86277729 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 172295810 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 261405 # Number of ticks simulated (Tick)
finalTick 2506600224 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7960927 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 3114028 # Number of instructions simulated (Count)
simOps 6222138 # Number of ops (including micro ops) simulated (Count)
hostInstRate 94507678 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 188789914 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3592 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3592 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 16 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 16 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 123272.671200 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 123272.671200 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.577327 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 123272.671200 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 123272.671200 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.577327 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 785 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.786573 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.271338 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2091 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2049 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 85 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 203 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.610191 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.320327 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 15 1.91% 1.91% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 183 23.31% 25.22% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 163 20.76% 45.99% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 237 30.19% 76.18% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 115 14.65% 90.83% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 66 8.41% 99.24% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 4 0.51% 99.75% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 1 0.13% 99.87% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 1 0.13% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 1 100.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1146 55.93% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 678 33.09% 89.02% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 225 10.98% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2049 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.610191 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 1 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.000488 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4884 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2177 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2041 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2050 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 4 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 694 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 233 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 467 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 123 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 120 99.17% 99.17% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 1 0.83% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 121 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 8 100.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 8 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 1 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 1 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 113 99.12% 99.12% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 1 0.88% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 114 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 1 100.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 1 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 121 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 121 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 0.00% 0.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 1 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 1 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 120 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 120 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 1 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 1 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 121 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 120 99.17% 99.17% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 1 0.83% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 85 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 1 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.589909 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.689695 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 112 14.49% 14.49% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 329 42.56% 57.05% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 109 14.10% 71.15% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 1 0.13% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 108 13.97% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 114 14.75% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1116 55.74% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 664 33.17% 88.91% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.09% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 2002 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 114 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 998 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 2002 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 998 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 2002 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.786573 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.271338 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 886 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 2002 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 664 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1116 55.74% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 664 33.17% 88.91% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.09% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 2002 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 112 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 109 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 408 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 24 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 242 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 2 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 118 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2115 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2045 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 114 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 678 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 225 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.605096 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 565 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 900 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2482 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1591 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 903 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1133 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 121 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 783 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 4 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 2 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.nisnDist::samples 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.768153 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.399018 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 424 54.01% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 64 8.15% 62.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 62.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 55 7.01% 69.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 1 0.13% 69.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 54 6.88% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 187 23.82% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1083 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.379618 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 121 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.154140 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 2 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 10 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2091 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 694 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 233 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 1 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2044 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2041 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1623 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1748 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.600000 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.928490 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 452 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 29 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 1 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 10 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2.001506 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 0.038808 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 664 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 678 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 225 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 2 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 2 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 10 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 235 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 399 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2109 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.LQFullEvents 369 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 4092 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7718 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2572 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 192 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 953 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2746 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4187 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 998 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 2002 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 2653959051 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7873562 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 3297029 # Number of instructions simulated (Count)
simOps 6588281 # Number of ops (including micro ops) simulated (Count)
hostInstRate 100006946 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 199772006 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 2801316879 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7910150 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 3480031 # Number of instructions simulated (Count)
simOps 6954425 # Number of ops (including micro ops) simulated (Count)
hostInstRate 106017700 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 211805598 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 261405 # Number of ticks simulated (Tick)
finalTick 2948677371 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7876966 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 3663032 # Number of instructions simulated (Count)
simOps 7320573 # Number of ops (including micro ops) simulated (Count)
hostInstRate 110017480 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 219817224 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3592 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3592 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 16 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 16 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 785 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.786573 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.271338 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2091 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2048 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 87 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 209 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.608917 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.318499 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 15 1.91% 1.91% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 183 23.31% 25.22% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 163 20.76% 45.99% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 237 30.19% 76.18% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 116 14.78% 90.96% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 65 8.28% 99.24% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 4 0.51% 99.75% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 1 0.13% 99.87% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 1 0.13% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 1 100.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1145 55.91% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 678 33.11% 89.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 225 10.99% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2048 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.608917 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 1 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.000488 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4883 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2179 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2042 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2049 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 3 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 694 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 233 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 467 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 123 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 120 99.17% 99.17% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 1 0.83% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 121 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 8 100.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 8 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 1 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 1 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 113 99.12% 99.12% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 1 0.88% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 114 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 1 100.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 1 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 121 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 121 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 0.00% 0.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 1 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 1 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 120 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 120 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 1 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 1 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 121 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 120 99.17% 99.17% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 1 0.83% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 87 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 1 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.589909 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.689695 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 112 14.49% 14.49% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 329 42.56% 57.05% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 109 14.10% 71.15% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 1 0.13% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 108 13.97% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 114 14.75% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1116 55.74% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 664 33.17% 88.91% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.09% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 2002 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 114 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 998 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 2002 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 998 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 2002 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.786573 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.271338 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 886 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 2002 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 664 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1116 55.74% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 664 33.17% 88.91% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.09% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 2002 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 112 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 109 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 408 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 24 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 242 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 2 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 118 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2115 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2046 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 114 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 678 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 225 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.606369 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 565 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 902 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2484 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1592 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 903 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1133 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 121 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 783 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 4 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 2 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.nisnDist::samples 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.768153 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.400518 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 424 54.01% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 65 8.28% 62.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 62.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 53 6.75% 69.04% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 1 0.13% 69.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.01% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 187 23.82% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1084 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.380892 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 121 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.154140 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 2 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 10 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2091 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 694 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 233 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 1 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2045 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2042 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1622 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1747 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.601274 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.928449 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 452 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 30 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 1 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 10 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2.001506 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 0.038808 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 664 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 678 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 225 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 2 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 2 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 2 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 10 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 235 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 399 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2108 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.LQFullEvents 370 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 4086 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7708 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2569 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 193 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 957 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2748 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4189 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 998 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 2002 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 3096035865 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7821202 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 3846033 # Number of instructions simulated (Count)
simOps 7686716 # Number of ops (including micro ops) simulated (Count)
hostInstRate 115774624 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 231269850 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 3243393693 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7881957 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4029035 # Number of instructions simulated (Count)
simOps 8052860 # Number of ops (including micro ops) simulated (Count)
hostInstRate 122336643 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 244344449 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 261405 # Number of ticks simulated (Tick)
finalTick 3390754185 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7770198 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4212036 # Number of instructions simulated (Count)
simOps 8419008 # Number of ops (including micro ops) simulated (Count)
hostInstRate 124804765 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 249370812 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3592 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3592 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 16 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 16 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 785 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.786573 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.271338 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2098 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2037 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 89 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 219 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.594904 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.315711 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 15 1.91% 1.91% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 186 23.69% 25.61% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 163 20.76% 46.37% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 237 30.19% 76.56% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 115 14.65% 91.21% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 63 8.03% 99.24% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 4 0.51% 99.75% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 1 0.13% 99.87% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 1 0.13% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 1 100.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1141 56.01% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 56.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 672 32.99% 89.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 224 11.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2037 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.594904 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 1 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.000491 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4859 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2188 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2030 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2038 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 2 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 696 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 233 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 468 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 122 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 120 99.17% 99.17% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 1 0.83% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 121 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 8 100.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 8 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 1 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 1 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 113 99.12% 99.12% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 1 0.88% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 114 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 1 100.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 1 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 121 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 121 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 0.00% 0.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 1 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 1 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 120 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 120 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 1 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 1 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 121 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 120 99.17% 99.17% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 1 0.83% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 89 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 1 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.589909 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.689695 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 112 14.49% 14.49% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 329 42.56% 57.05% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 109 14.10% 71.15% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 1 0.13% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 108 13.97% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 114 14.75% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1116 55.74% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 664 33.17% 88.91% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.09% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 2002 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 114 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 998 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 2002 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 998 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 2002 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.786573 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.271338 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 886 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 2002 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 664 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1116 55.74% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 664 33.17% 88.91% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.09% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 2002 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 112 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 109 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 408 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 24 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 242 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 2 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 118 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2115 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2034 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 113 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 673 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 223 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.591083 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 560 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 896 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2463 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1585 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 896 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1125 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 121 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 783 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 4 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 2 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.nisnDist::samples 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.768153 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.399018 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 424 54.01% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 64 8.15% 62.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 62.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 55 7.01% 69.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 1 0.13% 69.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 54 6.88% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 187 23.82% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1083 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.379618 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 121 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.154140 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 2 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 10 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2098 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 696 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 233 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 1 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2033 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2030 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1613 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1732 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.585987 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.931293 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 447 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 31 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 1 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 10 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2.001506 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 0.038808 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 664 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 673 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 223 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 2 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 2 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 2 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 10 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 235 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 399 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2106 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.LQFullEvents 370 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 4084 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7702 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2566 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 193 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 957 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2750 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4199 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 998 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 2002 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 3538112346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7812936 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4395037 # Number of instructions simulated (Count)
simOps 8785151 # Number of ops (including micro ops) simulated (Count)
hostInstRate 132213375 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 264207122 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 783216 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 783216 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 783216 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 783216 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358161 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 3685470174 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7856826 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4578039 # Number of instructions simulated (Count)
simOps 9151295 # Number of ops (including micro ops) simulated (Count)
hostInstRate 138539537 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 276858928 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 3832828002 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7875479 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4761041 # Number of instructions simulated (Count)
simOps 9517439 # Number of ops (including micro ops) simulated (Count)
hostInstRate 144335203 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 288442205 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 3980188494 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7881057 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 4944042 # Number of instructions simulated (Count)
simOps 9883587 # Number of ops (including micro ops) simulated (Count)
hostInstRate 149905764 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 299566181 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2001 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2000 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.570694 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.207341 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.59% 46.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 249 32.01% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 112 14.40% 92.93% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 55 7.07% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1111 55.55% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.35% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2000 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.570694 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4779 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2001 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2000 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2000 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 667 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 251 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2008 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2001 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.571979 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1555 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.336667 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 445 57.20% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 56 7.20% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 54 6.94% 71.34% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.34% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 56 7.20% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.47% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1001 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.286632 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2001 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 667 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2000 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2000 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570694 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2008 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3903 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7362 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2454 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 975 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3999 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 4127546988 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.04 # Real time elapsed on the host (Second)
hostTickRate 6682706 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 5127043 # Number of instructions simulated (Count)
simOps 10249730 # Number of ops (including micro ops) simulated (Count)
hostInstRate 132031392 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 263889447 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 4274904816 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7838024 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 5310045 # Number of instructions simulated (Count)
simOps 10615874 # Number of ops (including micro ops) simulated (Count)
hostInstRate 160167858 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 320092688 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 4422265308 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7796858 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 5493046 # Number of instructions simulated (Count)
simOps 10982022 # Number of ops (including micro ops) simulated (Count)
hostInstRate 164644846 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 329078928 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1999 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2000 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.570694 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.206275 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 167 21.47% 46.40% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 251 32.26% 78.66% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.93% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 55 7.07% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1111 55.55% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.55% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.35% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2000 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.570694 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4780 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1999 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2001 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2000 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 667 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 417 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2002 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.573265 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1556 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.560411 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.330693 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 446 57.33% 57.33% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.33% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.07% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.40% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.59% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.59% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.07% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 166 21.34% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 996 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.280206 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1999 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 667 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2001 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2001 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.571979 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 417 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 1998 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 389 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3885 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7326 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2442 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 962 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3991 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 4569623802 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7831855 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 5676047 # Number of instructions simulated (Count)
simOps 11348165 # Number of ops (including micro ops) simulated (Count)
hostInstRate 171269636 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 342307101 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 4716981630 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7866142 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 5859049 # Number of instructions simulated (Count)
simOps 11714309 # Number of ops (including micro ops) simulated (Count)
hostInstRate 177541559 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 354850024 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 4864342122 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7897875 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6042050 # Number of instructions simulated (Count)
simOps 12080457 # Number of ops (including micro ops) simulated (Count)
hostInstRate 183598712 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 366964064 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2005 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2002 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.573265 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210382 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 195 25.06% 25.06% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 165 21.21% 46.27% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 251 32.26% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.80% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.20% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1113 55.59% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.32% 88.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2002 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.573265 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4782 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2005 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2001 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2002 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 668 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 445 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 417 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2002 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.573265 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1556 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.330490 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.07% 57.07% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.07% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 56 7.20% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 56 7.20% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 166 21.34% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1000 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285347 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2005 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 668 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2001 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2001 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1584 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1696 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.571979 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.933962 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 138 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 417 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2006 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 390 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3902 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7358 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2452 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 975 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4001 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 5011700949 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7905075 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6225051 # Number of instructions simulated (Count)
simOps 12446600 # Number of ops (including micro ops) simulated (Count)
hostInstRate 189556973 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 378880399 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 5159058777 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7733076 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6408053 # Number of instructions simulated (Count)
simOps 12812744 # Number of ops (including micro ops) simulated (Count)
hostInstRate 190795361 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 381388421 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 259074 # Number of ticks simulated (Tick)
finalTick 5306419269 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7856203 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6591054 # Number of instructions simulated (Count)
simOps 13178892 # Number of ops (including micro ops) simulated (Count)
hostInstRate 198987229 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 397733273 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 446 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 446 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 446 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 446 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 223 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 223 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3568 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3568 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
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board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 472.779925 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 778 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.778000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285347 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2003 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2001 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571979 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.209395 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.94% 24.94% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.59% 46.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 249 32.01% 78.53% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.27% 92.80% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.20% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 778 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1112 55.57% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 667 33.33% 88.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2001 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571979 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4780 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2003 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2000 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2001 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 668 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 223 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 445 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 112 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 112 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.569409 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.665561 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 334 42.93% 57.20% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.27% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.47% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.27% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.73% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.27% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 778 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.53% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.53% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 667 33.37% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1999 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 1000 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1999 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 1000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1999 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.778000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285347 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 889 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1999 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 667 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.53% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.53% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 667 33.37% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1999 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 251 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2008 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2001 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 667 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.571979 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 890 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2447 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1555 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 889 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1111 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 778 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.570694 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335124 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 445 57.20% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.07% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.27% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.20% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.47% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.07% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.53% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.47% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 778 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.284062 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142674 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2003 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 668 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 223 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2000 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2000 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1585 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1697 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570694 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934001 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 667 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 667 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 667 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 223 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2008 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3904 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7361 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2453 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3889 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2666 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3999 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 1000 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1999 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 5453778096 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.04 # Real time elapsed on the host (Second)
hostTickRate 7262294 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6774055 # Number of instructions simulated (Count)
simOps 13545035 # Number of ops (including micro ops) simulated (Count)
hostInstRate 189537073 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 378860903 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358827 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 5601135924 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7870928 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 6957057 # Number of instructions simulated (Count)
simOps 13911179 # Number of ops (including micro ops) simulated (Count)
hostInstRate 210941360 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 421691443 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122091.144000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122091.144000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 471.866245 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 261405 # Number of ticks simulated (Tick)
finalTick 5748496416 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7811062 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 7140058 # Number of instructions simulated (Count)
simOps 14277327 # Number of ops (including micro ops) simulated (Count)
hostInstRate 212413221 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 424541392 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 449 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 449 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 449 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 449 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 226 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 226 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 223 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 223 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3592 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3592 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.switch.core.inst 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.switch.core.inst 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 2 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.switch.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.switch.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.switch.core.inst 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 2 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.switch.core.inst 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 16 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 16 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 123666.513600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 123666.513600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.083964 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 782550 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 785 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.786573 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.271338 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 2091 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 2048 # Number of instructions issued (Count)
board.processor.switch.core.squashedInstsExamined 87 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.switch.core.squashedOperandsExamined 209 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.switch.core.numIssuedDist::samples 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.608917 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.318499 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 15 1.91% 1.91% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 183 23.31% 25.22% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 163 20.76% 45.99% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 237 30.19% 76.18% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 116 14.78% 90.96% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 65 8.28% 99.24% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 4 0.51% 99.75% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 1 0.13% 99.87% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 1 0.13% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 785 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 1 100.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1145 55.91% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 678 33.11% 89.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 225 10.99% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 2048 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.608917 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 1 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0.000488 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4883 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 2179 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 2042 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 2049 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 3 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 694 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 233 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 467 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 123 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 120 99.17% 99.17% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 1 0.83% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 121 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 8 100.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 8 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 1 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 1 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 113 99.12% 99.12% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 1 0.88% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 114 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 1 100.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 1 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 121 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 121 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 0.00% 0.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 1 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 1 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 120 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 120 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 1 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 1 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 121 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 120 99.17% 99.17% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 1 0.83% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 121 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.commitSquashedInsts 87 # The number of squashed insts skipped by commit (Count)
board.processor.switch.core.commit.branchMispredicts 1 # The number of times a branch was mispredicted (Count)
board.processor.switch.core.commit.numCommittedDist::samples 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.589909 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.689695 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 112 14.49% 14.49% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 329 42.56% 57.05% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 109 14.10% 71.15% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 1 0.13% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.28% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 108 13.97% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.25% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 114 14.75% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 773 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1116 55.74% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.74% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 664 33.17% 88.91% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.09% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 2002 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 114 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 998 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 2002 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 998 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 2002 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.786573 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.271338 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 886 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 2002 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 664 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1116 55.74% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.74% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 664 33.17% 88.91% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.09% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 2002 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 113 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 112 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 109 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 408 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.runCycles 24 # Number of cycles decode is running (Cycle)
board.processor.switch.core.decode.unblockCycles 242 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.squashCycles 2 # Number of cycles decode is squashing (Cycle)
board.processor.switch.core.decode.branchResolved 118 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2115 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 2046 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 114 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 678 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 225 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.606369 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 565 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 902 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2484 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1592 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 903 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1133 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 121 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 783 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.squashCycles 4 # Number of cycles fetch has spent squashing (Cycle)
board.processor.switch.core.fetch.cacheLines 2 # Number of cache lines fetched (Count)
board.processor.switch.core.fetch.nisnDist::samples 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.768153 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.400518 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 424 54.01% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 54.01% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 65 8.28% 62.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 62.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 53 6.75% 69.04% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 1 0.13% 69.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.01% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 76.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 187 23.82% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 785 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 1084 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.380892 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 121 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.154140 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 2 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 10 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 2091 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 694 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 233 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 1 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 1 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 1 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 2045 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 2042 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1622 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1747 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.601274 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.928449 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 452 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 30 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 1 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 10 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2.001506 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::stdev 0.038808 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 664 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 664 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 678 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 225 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 1 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 2 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147360492 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.squashCycles 2 # Number of cycles rename is squashing (Cycle)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.blockCycles 10 # Number of cycles rename is blocking (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 235 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 399 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2108 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full (Count)
board.processor.switch.core.rename.LQFullEvents 370 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 4086 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7708 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2569 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.undoneMaps 193 # Number of HB maps that are undone due to squashing (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 957 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2748 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 4189 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 998 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 2002 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 5895854910 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7783791 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 7323059 # Number of instructions simulated (Count)
simOps 14643470 # Number of ops (including micro ops) simulated (Count)
hostInstRate 219364916 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 438440372 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 6.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 4.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 122484.986400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 122484.986400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 473.388394 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 0 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 0 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 0 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 779886 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::IprAccess 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.start.core.exec_context.thread_0.numCallsReturns 0 # Number of times a function call or return occured (Count)
board.processor.start.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.start.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.start.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.start.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.start.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.start.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start.core.workload.numSyscalls 0 # Number of system calls (Count)
board.processor.switch.core.numCycles 777 # Number of cpu cycles simulated (Cycle)
board.processor.switch.core.cpi 0.777778 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch.core.ipc 1.285714 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch.core.instsAdded 1998 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.switch.core.instsIssued 1998 # Number of instructions issued (Count)
board.processor.switch.core.numIssuedDist::samples 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::mean 2.571429 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::stdev 1.210077 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::0 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::1 194 24.97% 24.97% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::2 168 21.62% 46.59% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::3 248 31.92% 78.51% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::4 111 14.29% 92.79% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::5 56 7.21% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::min_value 1 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::max_value 5 # Number of insts issued each cycle (Count)
board.processor.switch.core.numIssuedDist::total 777 # Number of insts issued each cycle (Count)
board.processor.switch.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.switch.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntAlu 1110 55.56% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IntDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShift 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAes 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::Matrix 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.56% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemRead 666 33.33% 88.89% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::MemWrite 222 11.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.statIssuedInstType_0::total 1998 # Number of instructions issued per FU type, per thread (Count)
board.processor.switch.core.issueRate 2.571429 # Inst issue rate ((Count/Cycle))
board.processor.switch.core.fuBusy 0 # FU busy when requested (Count)
board.processor.switch.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.switch.core.intInstQueueReads 4772 # Number of integer instruction queue reads (Count)
board.processor.switch.core.intInstQueueWrites 1998 # Number of integer instruction queue writes (Count)
board.processor.switch.core.intInstQueueWakeupAccesses 1997 # Number of integer instruction queue wakeup accesses (Count)
board.processor.switch.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.switch.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.switch.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.switch.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.switch.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.switch.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.switch.core.intAluAccesses 1998 # Number of integer alu accesses (Count)
board.processor.switch.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.switch.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.switch.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.switch.core.MemDepUnit__0.insertedLoads 666 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.insertedStores 222 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingLoads 444 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__0.conflictingStores 111 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.switch.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.switch.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectCond 111 100.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.switch.core.branchPred.lookups_0::total 111 # Number of BP lookups (Count)
board.processor.switch.core.branchPred.squashes_0::NoBranch 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::Return 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallDirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::CallIndirect 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::DirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectCond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::IndirectUncond 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.squashes_0::total 0 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.switch.core.branchPred.corrected_0::NoBranch 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::Return 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallDirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::CallIndirect 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::DirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectCond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::IndirectUncond 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.corrected_0::total 0 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.switch.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.switch.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectCond 111 100.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::DirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.committed_0::total 111 # Number of branches finally committed (Count)
board.processor.switch.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.switch.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::BTB 111 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetProvider_0::total 111 # The component providing the target for taken branches (Count)
board.processor.switch.core.branchPred.targetWrong_0::NoBranch 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::Return 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallDirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::CallIndirect 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::DirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectCond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::IndirectUncond 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.targetWrong_0::total 0 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.switch.core.branchPred.condPredicted 111 # Number of conditional branches predicted (Count)
board.processor.switch.core.branchPred.condPredictedTaken 111 # Number of conditional branches predicted as taken (Count)
board.processor.switch.core.branchPred.condIncorrect 0 # Number of conditional branches incorrect (Count)
board.processor.switch.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.switch.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.switch.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.switch.core.branchPred.BTBLookups 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.BTBHits 111 # Number of BTB hits (Count)
board.processor.switch.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.switch.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.switch.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.switch.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.switch.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.switch.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.switch.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectCond 111 100.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.lookups::total 111 # Number of BTB lookups (Count)
board.processor.switch.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.switch.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.switch.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.switch.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.switch.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.switch.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.switch.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.switch.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.switch.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.switch.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.switch.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.switch.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.switch.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.switch.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.switch.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.switch.core.commit.numCommittedDist::samples 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::mean 2.571429 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::stdev 2.666682 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::0 111 14.29% 14.29% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::1 333 42.86% 57.14% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::2 111 14.29% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::3 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::4 0 0.00% 71.43% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::5 111 14.29% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::6 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::7 0 0.00% 85.71% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::8 111 14.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.numCommittedDist::total 777 # Number of insts commited each cycle (Count)
board.processor.switch.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.switch.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.switch.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.switch.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntAlu 1110 55.56% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IntDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShift 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAes 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::Matrix 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.56% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemRead 666 33.33% 88.89% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::MemWrite 222 11.11% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.switch.core.commit.committedInstType_0::total 1998 # Class of committed instruction (Count)
board.processor.switch.core.commit.commitEligibleSamples 111 # number cycles where commit BW limit reached (Cycle)
board.processor.switch.core.commitStats0.numInsts 999 # Number of instructions committed (thread level) (Count)
board.processor.switch.core.commitStats0.numOps 1998 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch.core.commitStats0.numInstsNotNOP 999 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch.core.commitStats0.numOpsNotNOP 1998 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch.core.commitStats0.cpi 0.777778 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch.core.commitStats0.ipc 1.285714 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch.core.commitStats0.numMemRefs 888 # Number of memory references committed (Count)
board.processor.switch.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch.core.commitStats0.numIntInsts 1998 # Number of integer instructions (Count)
board.processor.switch.core.commitStats0.numLoadInsts 666 # Number of load instructions (Count)
board.processor.switch.core.commitStats0.numStoreInsts 222 # Number of store instructions (Count)
board.processor.switch.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntAlu 1110 55.56% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::Matrix 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.56% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemRead 666 33.33% 88.89% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::MemWrite 222 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedInstType::total 1998 # Class of committed instruction. (Count)
board.processor.switch.core.commitStats0.committedControl::IsControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsDirectControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.commitStats0.committedControl::IsCondControl 111 # Class of control type instructions committed (Count)
board.processor.switch.core.decode.idleCycles 111 # Number of cycles decode is idle (Cycle)
board.processor.switch.core.decode.blockedCycles 416 # Number of cycles decode is blocked (Cycle)
board.processor.switch.core.decode.unblockCycles 250 # Number of cycles decode is unblocking (Cycle)
board.processor.switch.core.decode.branchResolved 111 # Number of times decode resolved a branch (Count)
board.processor.switch.core.decode.decodedInsts 2000 # Number of instructions handled by decode (Count)
board.processor.switch.core.executeStats0.numInsts 1997 # Number of executed instructions (Count)
board.processor.switch.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch.core.executeStats0.numBranches 111 # Number of branches executed (Count)
board.processor.switch.core.executeStats0.numLoadInsts 666 # Number of load instructions executed (Count)
board.processor.switch.core.executeStats0.numStoreInsts 222 # Number of stores executed (Count)
board.processor.switch.core.executeStats0.instRate 2.570142 # Inst execution rate ((Count/Cycle))
board.processor.switch.core.executeStats0.numCCRegReads 555 # Number of times the CC registers were read (Count)
board.processor.switch.core.executeStats0.numCCRegWrites 888 # Number of times the CC registers were written (Count)
board.processor.switch.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch.core.executeStats0.numIntRegReads 2442 # Number of times the integer registers were read (Count)
board.processor.switch.core.executeStats0.numIntRegWrites 1553 # Number of times the integer registers were written (Count)
board.processor.switch.core.executeStats0.numMemRefs 888 # Number of memory refs (Count)
board.processor.switch.core.executeStats0.numMiscRegReads 1110 # Number of times the Misc registers were read (Count)
board.processor.switch.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch.core.fetch.predictedBranches 111 # Number of branches that fetch has predicted taken (Count)
board.processor.switch.core.fetch.cycles 777 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.switch.core.fetch.nisnDist::samples 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::mean 2.574003 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::stdev 3.335995 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::0 444 57.14% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::1 0 0.00% 57.14% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::2 55 7.08% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::3 0 0.00% 64.22% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::4 56 7.21% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::5 0 0.00% 71.43% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::6 55 7.08% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::7 0 0.00% 78.51% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::8 167 21.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetch.nisnDist::total 777 # Number of instructions fetched each cycle (Total) (Count)
board.processor.switch.core.fetchStats0.numInsts 999 # Number of instructions fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch.core.fetchStats0.fetchRate 1.285714 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch.core.fetchStats0.numBranches 111 # Number of branches fetched (Count)
board.processor.switch.core.fetchStats0.branchRate 0.142857 # Number of branch fetches per cycle (Ratio)
board.processor.switch.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.switch.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.switch.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.switch.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.switch.core.iew.dispatchedInsts 1998 # Number of instructions dispatched to IQ (Count)
board.processor.switch.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.switch.core.iew.dispLoadInsts 666 # Number of dispatched load instructions (Count)
board.processor.switch.core.iew.dispStoreInsts 222 # Number of dispatched store instructions (Count)
board.processor.switch.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.switch.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.switch.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.switch.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.switch.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.switch.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.switch.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.switch.core.iew.instsToCommit 1997 # Cumulative count of insts sent to commit (Count)
board.processor.switch.core.iew.writebackCount 1997 # Cumulative count of insts written-back (Count)
board.processor.switch.core.iew.producerInst 1582 # Number of instructions producing a value (Count)
board.processor.switch.core.iew.consumerInst 1693 # Number of instructions consuming a value (Count)
board.processor.switch.core.iew.wbRate 2.570142 # Insts written-back per cycle ((Count/Cycle))
board.processor.switch.core.iew.wbFanout 0.934436 # Average fanout of values written-back ((Count/Count))
board.processor.switch.core.lsq0.forwLoads 444 # Number of loads that had data forwarded from stores (Count)
board.processor.switch.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.switch.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.switch.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.switch.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.switch.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.switch.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.switch.core.lsq0.loadToUse::samples 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::mean 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::0-9 666 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::max_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.lsq0.loadToUse::total 666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.switch.core.mmu.dtb.rdAccesses 666 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrAccesses 222 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.power_state.pwrStateResidencyTicks::OFF 147358494 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch.core.rename.idleCycles 139 # Number of cycles rename is idle (Cycle)
board.processor.switch.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.switch.core.rename.runCycles 222 # Number of cycles rename is running (Cycle)
board.processor.switch.core.rename.unblockCycles 416 # Number of cycles rename is unblocking (Cycle)
board.processor.switch.core.rename.renamedInsts 2000 # Number of instructions processed by rename (Count)
board.processor.switch.core.rename.LQFullEvents 388 # Number of times rename has blocked due to LQ full (Count)
board.processor.switch.core.rename.renamedOperands 3887 # Number of destination operands rename has renamed (Count)
board.processor.switch.core.rename.lookups 7329 # Number of register rename lookups that rename has made (Count)
board.processor.switch.core.rename.intLookups 2443 # Number of integer rename lookups (Count)
board.processor.switch.core.rename.committedMaps 3885 # Number of HB maps that are committed (Count)
board.processor.switch.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.switch.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.switch.core.rename.skidInsts 973 # count of insts added to the skid buffer (Count)
board.processor.switch.core.rob.reads 2664 # The number of ROB reads (Count)
board.processor.switch.core.rob.writes 3998 # The number of ROB writes (Count)
board.processor.switch.core.thread_0.numInsts 999 # Number of Instructions committed (Count)
board.processor.switch.core.thread_0.numOps 1998 # Number of Ops committed (Count)
board.processor.switch.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 258741 # Number of ticks simulated (Tick)
finalTick 6043212738 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 7810342 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 7506061 # Number of instructions simulated (Count)
simOps 15009614 # Number of ops (including micro ops) simulated (Count)
hostInstRate 225542698 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 450847471 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.switch.core.data 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.switch.core.data 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.switch.core.data 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.switch.core.data 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.switch.core.data 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.switch.core.data 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.switch.core.data 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.switch.core.data 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.start.core.data 498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.switch.core.data 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.start.core.data 0.972656 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.switch.core.data 0.027344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3552 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3552 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 512 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.start.core.inst 497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.switch.core.inst 15 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.start.core.inst 0.970703 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.switch.core.inst 0.029297 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 1 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2393 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 1 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 17 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 14 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.inst 813 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.start.core.data 1256 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.inst 184 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.switch.core.data 108 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000244 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.004150 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.003418 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.inst 0.198486 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.start.core.data 0.306641 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.inst 0.044922 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.switch.core.data 0.026367 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.584229 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 31 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2362 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 31 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2362 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.007568 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.576660 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 147357828 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>