---------- Begin Simulation Statistics ----------
simSeconds 0.000029 # Number of seconds simulated (Second)
simTicks 28638666 # Number of ticks simulated (Tick)
finalTick 28638666 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.08 # Real time elapsed on the host (Second)
hostTickRate 346429888 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3603724 # Number of bytes of host memory used (Byte)
simInsts 8700 # Number of instructions simulated (Count)
simOps 8710 # Number of ops (including micro ops) simulated (Count)
hostInstRate 105078 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 105188 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 3189 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 3189 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 3189 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 3189 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 230 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 230 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 230 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 230 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 10752237 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 10752237 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 10752237 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 10752237 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 3419 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 3419 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 3419 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 3419 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.067271 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.067271 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.067271 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.067271 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 46748.856522 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 46748.856522 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 46748.856522 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 46748.856522 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 1 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 1 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 60 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 60 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 60 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 60 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 170 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 170 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 42 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 170 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 212 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 8776548 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 8776548 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 1292601 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 8776548 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 10069149 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.049722 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.049722 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.049722 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.062006 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 51626.752941 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 51626.752941 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 30776.214286 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 51626.752941 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 47495.985849 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 2 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 42 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 42 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 1292601 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 1292601 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 30776.214286 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 30776.214286 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::processor.cores.core.data 10 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::total 10 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::processor.cores.core.data 10 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::total 10 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 1790 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 1790 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 102 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 102 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 5545449 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 5545449 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 1892 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 1892 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.053911 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.053911 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 54367.147059 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 54367.147059 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data 3 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total 3 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 99 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 99 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 5359968 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 5359968 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.052326 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.052326 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 54141.090909 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 54141.090909 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::processor.cores.core.data 10 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::total 10 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::processor.cores.core.data 10 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::total 10 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SwapReq.hits::processor.cores.core.data 12 # number of SwapReq hits (Count)
board.cache_hierarchy.l1dcaches.SwapReq.hits::total 12 # number of SwapReq hits (Count)
board.cache_hierarchy.l1dcaches.SwapReq.accesses::processor.cores.core.data 12 # number of SwapReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SwapReq.accesses::total 12 # number of SwapReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 1399 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 1399 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 128 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 128 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 5206788 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 5206788 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 1527 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 1527 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.083824 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.083824 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 40678.031250 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 40678.031250 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 57 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 57 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 71 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 71 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 3416580 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 3416580 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.046496 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.046496 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 48120.845070 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 48120.845070 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 170 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 149 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 28 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.187919 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.141414 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 36 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 71 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 107 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 156 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 6 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 134.549420 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 3433 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 212 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 16.193396 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 132534 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 32.017151 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 102.532269 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.125067 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.400517 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.525584 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 42 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 168 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 42 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 37 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 131 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.164062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.656250 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 27820 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 27820 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 3456 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 3456 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 3456 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 3456 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 466 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 466 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 466 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 466 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 21494151 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 21494151 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 21494151 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 21494151 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 3922 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 3922 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 3922 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 3922 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.118817 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.118817 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.118817 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.118817 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 46124.787554 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 46124.787554 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 46124.787554 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 46124.787554 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 466 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 466 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 466 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 466 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 21339306 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 21339306 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 21339306 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 21339306 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.118817 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.118817 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.118817 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.118817 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 45792.502146 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 45792.502146 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 45792.502146 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 45792.502146 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 209 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 3456 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 3456 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 466 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 466 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 21494151 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 21494151 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 3922 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 3922 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.118817 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.118817 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 46124.787554 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 46124.787554 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 466 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 466 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 21339306 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 21339306 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.118817 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.118817 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 45792.502146 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 45792.502146 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 466 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 175.485631 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 3921 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 465 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 8.432258 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 175.485631 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.685491 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.685491 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 163 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1 93 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 31841 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 31841 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.transDist::ReadResp 606 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::WritebackDirty 1 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::CleanEvict 210 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::HardPFReq 59 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExReq 71 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExResp 71 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadSharedReq 607 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 1140 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 426 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount::total 1566 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 29760 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 13632 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize::total 43392 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.snoops 59 # Total snoops (Count)
board.cache_hierarchy.l2bus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2bus.snoopFanout::samples 737 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::mean 0.002714 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::stdev 0.052058 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::0 735 99.73% 99.73% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::1 2 0.27% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::total 737 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.reqLayer0.occupancy 306933 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer0.occupancy 464867 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer1.occupancy 211788 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.snoop_filter.totRequests 889 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleRequests 212 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.totSnoops 1 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleSnoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches.prefetcher 7 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.inst 36 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.data 4 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::total 47 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches.prefetcher 7 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.inst 36 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.data 4 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::total 47 # number of overall hits (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches.prefetcher 35 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.inst 430 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.data 166 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::total 631 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches.prefetcher 35 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.inst 430 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.data 166 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::total 631 # number of overall misses (Count)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches.prefetcher 1244682 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.inst 20897415 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.data 8648343 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::total 30790440 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches.prefetcher 1244682 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.inst 20897415 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.data 8648343 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::total 30790440 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches.prefetcher 42 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.inst 466 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.data 170 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::total 678 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches.prefetcher 42 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.inst 466 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.data 170 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::total 678 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches.prefetcher 0.833333 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.inst 0.922747 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.data 0.976471 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::total 0.930678 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches.prefetcher 0.833333 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.inst 0.922747 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.data 0.976471 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::total 0.930678 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 35562.342857 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.inst 48598.639535 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.data 52098.451807 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::total 48796.259905 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 35562.342857 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.inst 48598.639535 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.data 52098.451807 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::total 48796.259905 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches.prefetcher 32 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores.core.inst 1 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::total 33 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches.prefetcher 32 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores.core.inst 1 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::total 33 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches.prefetcher 3 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.inst 429 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.data 166 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::total 598 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 3 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l2cache.prefetcher 46 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.inst 429 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.data 166 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::total 644 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 284382 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.inst 20696283 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.data 8593065 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::total 29573730 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 284382 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l2cache.prefetcher 2376754 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.inst 20696283 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.data 8593065 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::total 31950484 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.071429 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.inst 0.920601 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.data 0.976471 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::total 0.882006 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.071429 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.inst 0.920601 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.data 0.976471 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::total 0.949853 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 94794 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 48243.083916 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 51765.451807 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::total 49454.397993 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 94794 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 51668.565217 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 48243.083916 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 51765.451807 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::total 49612.552795 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::cache_hierarchy.l2cache.prefetcher 46 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::total 46 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.l2cache.prefetcher 2376754 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::total 2376754 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 51668.565217 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::total 51668.565217 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores.core.data 4 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::total 4 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores.core.data 67 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::total 67 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores.core.data 3354309 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::total 3354309 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores.core.data 71 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::total 71 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores.core.data 0.943662 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::total 0.943662 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 50064.313433 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::total 50064.313433 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 67 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::total 67 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 3331998 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::total 3331998 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.943662 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::total 0.943662 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 49731.313433 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::total 49731.313433 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches.prefetcher 7 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.inst 36 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::total 43 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::cache_hierarchy.l1dcaches.prefetcher 35 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.inst 430 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.data 99 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::total 564 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::cache_hierarchy.l1dcaches.prefetcher 1244682 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 20897415 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 5294034 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::total 27436131 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::cache_hierarchy.l1dcaches.prefetcher 42 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 466 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.data 99 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::total 607 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::cache_hierarchy.l1dcaches.prefetcher 0.833333 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.922747 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.data 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::total 0.929160 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches.prefetcher 35562.342857 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 48598.639535 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 53475.090909 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::total 48645.622340 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.l1dcaches.prefetcher 32 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::processor.cores.core.inst 1 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::total 33 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 3 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 429 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 99 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::total 531 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 284382 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 20696283 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 5261067 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::total 26241732 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.071429 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.920601 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::total 0.874794 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 94794 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 48243.083916 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 53142.090909 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::total 49419.457627 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.WritebackDirty.hits::writebacks 1 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.hits::total 1 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::total 1 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.prefetcher.demandMshrMisses 598 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIssued 143 # number of hwpf issued (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUseful 11 # number of useful prefetch (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2cache.prefetcher.accuracy 0.076923 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.coverage 0.018062 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInCache 16 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInMSHR 81 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2cache.prefetcher.pfLate 97 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIdentified 159 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2cache.prefetcher.pfBufferHit 9 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedDemand 5 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2cache.prefetcher.pfSpanPage 1 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.tags.tagsInUse 351.385478 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2cache.tags.totalRefs 901 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.sampledRefs 643 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.avgRefs 1.401244 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2cache.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 2.529639 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l2cache.prefetcher 34.491931 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.inst 213.705642 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.data 100.658266 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.000618 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l2cache.prefetcher 0.008421 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.inst 0.052174 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.data 0.024575 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::total 0.085787 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1022 49 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1024 594 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::1 49 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::0 190 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::1 404 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1022 0.011963 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1024 0.145020 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.tagAccesses 14867 # Number of tag accesses (Count)
board.cache_hierarchy.l2cache.tags.dataAccesses 14867 # Number of data accesses (Count)
board.cache_hierarchy.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 576 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 67 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 67 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 576 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 1286 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::total 1286 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 1286 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 41152 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::total 41152 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 41152 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 643 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 643 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 643 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 224600 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 529570 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 643 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 4.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l2cache.prefetcher::samples 45.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 428.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 166.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000735864 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 1286 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 643 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 643 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 1.26 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 643 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 498 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 93 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 17 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 22 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 1 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 41152 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 1436938438.40352058 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 28589715 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 44463.01 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l2cache.prefetcher 2880 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 27392 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 10624 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 8938963.846989240497 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l2cache.prefetcher 100563343.278628960252 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 956469131.627848863602 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 370966999.650053501129 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 4 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l2cache.prefetcher 45 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 428 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 166 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 179134 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l2cache.prefetcher 1304393 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 9077312 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 4084861 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 44783.50 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l2cache.prefetcher 28986.51 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 21208.67 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 24607.60 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l2cache.prefetcher 2880 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 27392 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 10624 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 41152 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 27392 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 27392 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 4 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l2cache.prefetcher 45 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 428 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 166 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 643 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 8938964 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l2cache.prefetcher 100563343 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 956469132 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 370967000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 1436938438 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 956469132 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 956469132 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 8938964 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l2cache.prefetcher 100563343 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 956469132 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 370967000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 1436938438 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 643 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 42 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 39 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 54 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 2 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 22 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 44 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 32 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 48 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 30 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 17 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 51 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 5 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 74 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 40 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 48 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 29 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 9 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 5 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 17 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 6 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 11 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 3398344 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 2142476 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 14645700 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 5285.14 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 22777.14 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 558 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 86.78 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 73 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 504.986301 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 350.186265 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 364.943698 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 10 13.70% 13.70% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 11 15.07% 28.77% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 14 19.18% 47.95% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 5 6.85% 54.79% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 6 8.22% 63.01% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 3 4.11% 67.12% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 4 5.48% 72.60% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 4 5.48% 78.08% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 16 21.92% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 73 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 41152 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 1436.938438 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 7.48 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 7.48 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 86.78 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 84206.304000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 126633.326400 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 1264478.006400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 2027566.648800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 13468622.395200 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 49756.089600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 17021262.770400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 594.345518 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 69172 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 1050000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 27519494 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 48340.656000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 74328.256800 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 499208.236800 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 2027566.648800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 13258310.553600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 194945.990400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 16102700.342400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 562.271313 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 514535 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 1050000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 27074131 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 86002 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 9.885287 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.101160 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 21 0.58% 0.58% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 261 7.23% 7.81% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 323 8.95% 16.76% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 78 2.16% 18.92% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 2534 70.21% 89.14% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 369 10.22% 99.36% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.36% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 23 0.64% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 3609 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 10 0.58% 0.58% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 106 6.13% 6.71% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 194 11.23% 17.94% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 48 2.78% 20.72% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 1118 64.70% 85.42% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 243 14.06% 99.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 99.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 9 0.52% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 1728 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 10 1.72% 1.72% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 0 0.00% 1.72% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 86 14.78% 16.49% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 27 4.64% 21.13% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 378 64.95% 86.08% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 68 11.68% 97.77% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 97.77% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 13 2.23% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 582 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 10 0.53% 0.53% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 155 8.25% 8.78% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 129 6.87% 15.65% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 30 1.60% 17.24% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 1415 75.31% 92.55% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 126 6.71% 99.25% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 99.25% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 14 0.75% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 1879 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 10 1.72% 1.72% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 1.72% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 86 14.78% 16.49% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 27 4.64% 21.13% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 378 64.95% 86.08% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 68 11.68% 97.77% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 97.77% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 13 2.23% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 582 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond 139 100.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total 139 # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch 10 2.26% 2.26% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return 0 0.00% 2.26% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect 86 19.41% 21.67% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect 27 6.09% 27.77% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond 239 53.95% 81.72% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond 68 15.35% 97.07% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond 0 0.00% 97.07% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond 13 2.93% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total 443 # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 2646 73.32% 73.32% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 699 19.37% 92.68% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 261 7.23% 99.92% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 3 0.08% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 3609 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 523 91.43% 91.43% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 49 8.57% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 572 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 2555 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 728 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 582 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 181 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups 3609 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 483 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 958 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.265447 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 393 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 101 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 3 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 98 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 21 0.58% 0.58% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 261 7.23% 7.81% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 323 8.95% 16.76% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 78 2.16% 18.92% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 2534 70.21% 89.14% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 369 10.22% 99.36% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.36% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 23 0.64% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 3609 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 21 0.79% 0.79% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 261 9.85% 10.64% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 271 10.22% 20.86% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 78 2.94% 23.80% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 1717 64.77% 88.57% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 280 10.56% 99.13% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 99.13% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 23 0.87% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 2651 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 86 17.81% 17.81% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 17.81% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 329 68.12% 85.92% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 68 14.08% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 483 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 86 17.81% 17.81% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 17.81% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 329 68.12% 85.92% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 68 14.08% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 483 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 101 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 3 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 98 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 40 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 141 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 507 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 503 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 348 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 155 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 155 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commitStats0.numInsts 8700 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 8710 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 9.885287 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.101160 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 31 0.36% 0.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 5508 63.24% 63.59% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3 0.03% 63.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 10 0.11% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 63.74% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 1618 18.58% 82.32% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 1528 17.54% 99.86% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 99.86% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 12 0.14% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 8710 # Class of committed instruction. (Count)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 1805 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch2.intInstructions 10026 # Number of integer instructions successfully decoded (Count)
board.processor.cores.core.fetch2.fpInstructions 0 # Number of floating point instructions successfully decoded (Count)
board.processor.cores.core.fetch2.vecInstructions 0 # Number of SIMD instructions successfully decoded (Count)
board.processor.cores.core.fetch2.loadInstructions 3172 # Number of memory load instructions successfully decoded (Count)
board.processor.cores.core.fetch2.storeInstructions 2195 # Number of memory store instructions successfully decoded (Count)
board.processor.cores.core.fetch2.amoInstructions 0 # Number of memory atomic instructions successfully decoded (Count)
board.processor.cores.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.branchRate 0 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.mmu.dtb.readHits 0 # read hits (Count)
board.processor.cores.core.mmu.dtb.readMisses 0 # read misses (Count)
board.processor.cores.core.mmu.dtb.readAccesses 0 # read accesses (Count)
board.processor.cores.core.mmu.dtb.writeHits 0 # write hits (Count)
board.processor.cores.core.mmu.dtb.writeMisses 0 # write misses (Count)
board.processor.cores.core.mmu.dtb.writeAccesses 0 # write accesses (Count)
board.processor.cores.core.mmu.dtb.hits 0 # Total TLB (read and write) hits (Count)
board.processor.cores.core.mmu.dtb.misses 0 # Total TLB (read and write) misses (Count)
board.processor.cores.core.mmu.dtb.accesses 0 # Total TLB (read and write) accesses (Count)
board.processor.cores.core.mmu.dtb.walker.num_4kb_walks 0 # Completed page walks with 4KB pages (Count)
board.processor.cores.core.mmu.dtb.walker.num_64kb_walks 0 # Completed page walks with 64KB pages (Count)
board.processor.cores.core.mmu.dtb.walker.num_2mb_walks 0 # Completed page walks with 2MB pages (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.readHits 0 # read hits (Count)
board.processor.cores.core.mmu.itb.readMisses 0 # read misses (Count)
board.processor.cores.core.mmu.itb.readAccesses 0 # read accesses (Count)
board.processor.cores.core.mmu.itb.writeHits 0 # write hits (Count)
board.processor.cores.core.mmu.itb.writeMisses 0 # write misses (Count)
board.processor.cores.core.mmu.itb.writeAccesses 0 # write accesses (Count)
board.processor.cores.core.mmu.itb.hits 0 # Total TLB (read and write) hits (Count)
board.processor.cores.core.mmu.itb.misses 0 # Total TLB (read and write) misses (Count)
board.processor.cores.core.mmu.itb.accesses 0 # Total TLB (read and write) accesses (Count)
board.processor.cores.core.mmu.itb.walker.num_4kb_walks 0 # Completed page walks with 4KB pages (Count)
board.processor.cores.core.mmu.itb.walker.num_64kb_walks 0 # Completed page walks with 64KB pages (Count)
board.processor.cores.core.mmu.itb.walker.num_2mb_walks 0 # Completed page walks with 2MB pages (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 28638666 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 8700 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 8710 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 11 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
board.processor.cores.core.idleCycles 71340 # Total number of cycles that the object has spent stopped (Unspecified)
board.processor.cores.core.tickCycles 14662 # Number of cycles that the object actually ticked (Unspecified)
---------- End Simulation Statistics ----------