[board]
type=ArmSystem
children=cache_hierarchy clk_domain dvfs_handler iobridge iobus memory pci_devices processor realview release terminal vncserver voltage_domain workload
auto_reset_addr=true
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=true
external_memory_ranges=
gic_cpu_addr=0
have_large_asid_64=false
highest_el_is_64=true
init_param=0
m5ops_base=268500992
mem_mode=timing
mem_ranges=2147483648:3221225472
memories=board.memory.mem_ctrl.dram board.realview.bootmem board.realview.flash0 board.realview.flash1 board.realview.non_trusted_sram board.realview.trusted_dram board.realview.trusted_sram board.realview.vram
mmap_using_noreserve=false
multi_proc=false
multi_thread=false
num_work_ids=16
phys_addr_range_64=40
readfile=
redirect_paths=
release=board.release
reset_addr=0
semihosting=Null
shadow_rom_ranges=
shared_backstore=
sme_vl=1
sve_vl=1
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[0]

[board.cache_hierarchy]
type=SubSystem
children=dptw_caches iocache iptw_caches l1dcaches l1icaches membus
eventq_index=0
thermal_domain=Null

[board.cache_hierarchy.dptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.dptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.mmu.dtb_walker.port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[5]

[board.cache_hierarchy.dptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.dptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.dptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.dptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.dptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.dptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iocache]
type=Cache
children=power_state replacement_policy tags
addr_ranges=2147483648:3221225472
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=50
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iocache.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iocache.replacement_policy
response_latency=50
sequential_access=false
size=1024
system=board
tag_latency=50
tags=board.cache_hierarchy.iocache.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.iobus.mem_side_ports[19]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[1]

[board.cache_hierarchy.iocache.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iocache.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iocache.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iocache.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iocache.tags.power_state
replacement_policy=board.cache_hierarchy.iocache.replacement_policy
sequential_access=false
size=1024
system=board
tag_latency=50
warmup_percentage=0

[board.cache_hierarchy.iocache.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=1024

[board.cache_hierarchy.iocache.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.iptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.mmu.itb_walker.port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[4]

[board.cache_hierarchy.iptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.iptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.iptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.power_state
prefetcher=board.cache_hierarchy.l1dcaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
response_latency=1
sequential_access=false
size=65536
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.dcache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[3]

[board.cache_hierarchy.l1dcaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1dcaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1dcaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1dcaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
sequential_access=false
size=65536
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1dcaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=65536

[board.cache_hierarchy.l1dcaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.power_state
prefetcher=board.cache_hierarchy.l1icaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
response_latency=1
sequential_access=false
size=65536
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.icache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[2]

[board.cache_hierarchy.l1icaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1icaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1icaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1icaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
sequential_access=false
size=65536
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1icaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=65536

[board.cache_hierarchy.l1icaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.system_port board.cache_hierarchy.iocache.mem_side board.cache_hierarchy.l1icaches.mem_side board.cache_hierarchy.l1dcaches.mem_side board.cache_hierarchy.iptw_caches.mem_side board.cache_hierarchy.dptw_caches.mem_side
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.iobridge.cpu_side_port board.realview.bootmem.port board.realview.trusted_sram.port board.realview.trusted_dram.port board.realview.non_trusted_sram.port board.realview.flash0.port board.realview.generic_timer_mem.pio board.realview.el2_watchdog.pio board.realview.trusted_watchdog.pio board.realview.system_watchdog.pio board.realview.generic_timer_mem.frames0.pio board.realview.generic_timer_mem.frames1.pio board.realview.gic.pio board.memory.mem_ctrl.port

[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default

[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board

[board.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.voltage_domain

[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000

[board.iobridge]
type=Bridge
children=power_state
clk_domain=board.clk_domain
delay=50000
eventq_index=0
power_model=
power_state=board.iobridge.power_state
ranges=201326592:536870912 1073741824:2147483648 274877906944:549755813888
req_size=16
resp_size=16
cpu_side_port=board.cache_hierarchy.membus.mem_side_ports[0]
mem_side_port=board.iobus.cpu_side_ports[0]

[board.iobridge.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.iobus]
type=NoncoherentXBar
children=badaddr_responder power_state
clk_domain=board.clk_domain
eventq_index=0
forward_latency=1
frontend_latency=2
header_latency=1
power_model=
power_state=board.iobus.power_state
response_latency=2
use_default_range=false
width=16
cpu_side_ports=board.iobridge.mem_side_port board.realview.clcd.dma board.pci_devices.dma
default=board.iobus.badaddr_responder.pio
mem_side_ports=board.realview.flash1.port board.realview.vram.port board.realview.realview_io.pio board.realview.kmi0.pio board.realview.kmi1.pio board.realview.watchdog.pio board.realview.rtc.pio board.realview.pci_host.pio board.realview.energy_ctrl.pio board.realview.pwr_ctrl.pio board.realview.vio0.pio board.realview.vio1.pio board.realview.uart0.pio board.realview.uart1.pio board.realview.uart2.pio board.realview.uart3.pio board.realview.clcd.pio board.realview.sp810_fake.pio board.pci_devices.pio board.cache_hierarchy.iocache.cpu_side

[board.iobus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.iobus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.iobus.default

[board.iobus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.iobus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.memory]
type=SubSystem
children=mem_ctrl
eventq_index=0
thermal_domain=Null

[board.memory.mem_ctrl]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=               
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[13]

[board.memory.mem_ctrl.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl.dram.power_state
range=2147483648:3221225472
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true

[board.memory.mem_ctrl.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.memory.mem_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.pci_devices]
type=PciVirtIO
children=BAR0 BAR1 BAR2 BAR3 BAR4 BAR5 power_state vio
BAR0=board.pci_devices.BAR0
BAR1=board.pci_devices.BAR1
BAR2=board.pci_devices.BAR2
BAR3=board.pci_devices.BAR3
BAR4=board.pci_devices.BAR4
BAR5=board.pci_devices.BAR5
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=255
Command=0
DeviceID=4096
ExpansionROM=0
HeaderType=0
InterruptLine=0
InterruptPin=1
LatencyTimer=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPDevStatus2=0
PXCAPLinkCap=0
PXCAPLinkCap2=0
PXCAPLinkCtrl=0
PXCAPLinkCtrl2=0
PXCAPLinkStatus=0
PXCAPLinkStatus2=0
PXCAPNextCapability=0
PXCAPRootCap=0
PXCAPRootCtrl=0
PXCAPRootStatus=0
PXCAPSlotCap=0
PXCAPSlotCap2=0
PXCAPSlotCtrl=0
PXCAPSlotCtrl2=0
PXCAPSlotStatus=0
PXCAPSlotStatus2=0
ProgIF=0
Revision=0
Status=0
SubClassCode=0
SubsystemID=0
SubsystemVendorID=6900
VendorID=6900
clk_domain=board.clk_domain
config_latency=20000
eventq_index=0
host=board.realview.pci_host
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
power_model=
power_state=board.pci_devices.power_state
sid=NullOpt
ssid=NullOpt
system=board
vio=board.pci_devices.vio
dma=board.iobus.cpu_side_ports[2]
pio=board.iobus.mem_side_ports[18]

[board.pci_devices.BAR0]
type=PciIoBar
eventq_index=0
size=4

[board.pci_devices.BAR1]
type=PciBarNone
eventq_index=0

[board.pci_devices.BAR2]
type=PciBarNone
eventq_index=0

[board.pci_devices.BAR3]
type=PciBarNone
eventq_index=0

[board.pci_devices.BAR4]
type=PciBarNone
eventq_index=0

[board.pci_devices.BAR5]
type=PciBarNone
eventq_index=0

[board.pci_devices.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.pci_devices.vio]
type=VirtIOBlock
children=image
byte_order=little
eventq_index=0
image=board.pci_devices.vio.image
queueSize=128
subsystem=0
system=board

[board.pci_devices.vio.image]
type=CowDiskImage
children=child
child=board.pci_devices.vio.image.child
eventq_index=0
image_file=
read_only=false
table_size=65536

[board.pci_devices.vio.image.child]
type=RawDiskImage
eventq_index=0
image_file=gem5/arm-ubuntu-24.04-img
read_only=true

[board.processor]
type=SubSystem
children=cores
eventq_index=0
thermal_domain=Null

[board.processor.cores]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null

[board.processor.cores.core]
type=BaseTimingSimpleCPU
children=decoder interrupts isa mmu power_state tracer
branchPred=Null
checker=Null
clk_domain=board.clk_domain
cpu_id=0
decoder=board.processor.cores.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=board.processor.cores.core.interrupts
isa=board.processor.cores.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.cores.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.cores.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=board
tracer=board.processor.cores.core.tracer
workload=
dcache_port=board.cache_hierarchy.l1dcaches.cpu_side
icache_port=board.cache_hierarchy.l1icaches.cpu_side

[board.processor.cores.core.decoder]
type=ArmDecoder
dvm_enabled=false
eventq_index=0
isa=board.processor.cores.core.isa

[board.processor.cores.core.interrupts]
type=ArmInterrupts
eventq_index=0

[board.processor.cores.core.isa]
type=ArmISA
children=release_se
decoderFlavor=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=15790086
id_aa64dfr1_el1=0
id_aa64isar0_el1=268435456
id_aa64isar1_el1=16846864
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=1052704
id_aa64mmfr2_el1=65552
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=285212672
id_isar6=1
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_mmfr4=0
impdef_nop=false
midr=0
mpamidr_el1=3746995439730032896
pmu=Null
release_se=board.processor.cores.core.isa.release_se
sme_vl_se=1
sve_vl_se=1
system=board

[board.processor.cores.core.isa.release_se]
type=ArmRelease
eventq_index=0
extensions=FEAT_AES FEAT_PMULL FEAT_SHA1 FEAT_SHA256 FEAT_CRC32 FEAT_LSE FEAT_RDM FEAT_F32MM FEAT_F64MM FEAT_SVE FEAT_I8MM FEAT_DOTPROD FEAT_FCMA FEAT_JSCVT FEAT_PAuth FEAT_FLAGM FEAT_FLAGM2 FEAT_SME TME

[board.processor.cores.core.mmu]
type=ArmMMU
children=dtb dtb_walker itb itb_walker l2_shared stage2_dtb stage2_dtb_walker stage2_itb stage2_itb_walker
dtb=board.processor.cores.core.mmu.dtb
dtb_walker=board.processor.cores.core.mmu.dtb_walker
eventq_index=0
itb=board.processor.cores.core.mmu.itb
itb_walker=board.processor.cores.core.mmu.itb_walker
release_se=board.processor.cores.core.isa.release_se
stage2_dtb=board.processor.cores.core.mmu.stage2_dtb
stage2_dtb_walker=board.processor.cores.core.mmu.stage2_dtb_walker
stage2_itb=board.processor.cores.core.mmu.stage2_itb
stage2_itb_walker=board.processor.cores.core.mmu.stage2_itb_walker
sys=board

[board.processor.cores.core.mmu.dtb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=64
entry_type=data
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.dtb.indexing_policy
is_stage2=false
next_level=board.processor.cores.core.mmu.l2_shared
partial_levels=
replacement_policy=board.processor.cores.core.mmu.dtb.replacement_policy
size=64
sys=board

[board.processor.cores.core.mmu.dtb.indexing_policy]
type=TLBSetAssociative
assoc=64
eventq_index=0
num_entries=64

[board.processor.cores.core.mmu.dtb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.dtb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.dtb_walker.power_state
sys=board
port=board.cache_hierarchy.dptw_caches.cpu_side

[board.processor.cores.core.mmu.dtb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.itb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=64
entry_type=instruction
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.itb.indexing_policy
is_stage2=false
next_level=board.processor.cores.core.mmu.l2_shared
partial_levels=
replacement_policy=board.processor.cores.core.mmu.itb.replacement_policy
size=64
sys=board

[board.processor.cores.core.mmu.itb.indexing_policy]
type=TLBSetAssociative
assoc=64
eventq_index=0
num_entries=64

[board.processor.cores.core.mmu.itb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.itb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.itb_walker.power_state
sys=board
port=board.cache_hierarchy.iptw_caches.cpu_side

[board.processor.cores.core.mmu.itb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.l2_shared]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=5
entry_type=unified
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.l2_shared.indexing_policy
is_stage2=false
next_level=Null
partial_levels=L2
replacement_policy=board.processor.cores.core.mmu.l2_shared.replacement_policy
size=1280
sys=board

[board.processor.cores.core.mmu.l2_shared.indexing_policy]
type=TLBSetAssociative
assoc=5
eventq_index=0
num_entries=1280

[board.processor.cores.core.mmu.l2_shared.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_dtb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=32
entry_type=data
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.stage2_dtb.indexing_policy
is_stage2=true
next_level=Null
partial_levels=
replacement_policy=board.processor.cores.core.mmu.stage2_dtb.replacement_policy
size=32
sys=board

[board.processor.cores.core.mmu.stage2_dtb.indexing_policy]
type=TLBSetAssociative
assoc=32
eventq_index=0
num_entries=32

[board.processor.cores.core.mmu.stage2_dtb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_dtb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.stage2_dtb_walker.power_state
sys=board

[board.processor.cores.core.mmu.stage2_dtb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.stage2_itb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=32
entry_type=instruction
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.stage2_itb.indexing_policy
is_stage2=true
next_level=Null
partial_levels=
replacement_policy=board.processor.cores.core.mmu.stage2_itb.replacement_policy
size=32
sys=board

[board.processor.cores.core.mmu.stage2_itb.indexing_policy]
type=TLBSetAssociative
assoc=32
eventq_index=0
num_entries=32

[board.processor.cores.core.mmu.stage2_itb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_itb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.stage2_itb_walker.power_state
sys=board

[board.processor.cores.core.mmu.stage2_itb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF

[board.processor.cores.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.cores.core.tracer.disassembler
eventq_index=0

[board.processor.cores.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0

[board.realview]
type=RealView
children=bootmem clcd clock24MHz clock32KHz dcc el2_watchdog energy_ctrl flash0 flash1 generic_timer generic_timer_mem gic io_voltage kmi0 kmi1 mcc non_trusted_sram pci_host pwr_ctrl realview_io rtc sp810_fake sys_counter system_watchdog trusted_dram trusted_sram trusted_watchdog uart0 uart1 uart2 uart3 vio0 vio1 vram watchdog
eventq_index=0
system=board

[board.realview.bootmem]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.bootmem.power_state
range=0:67108864
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[1]

[board.realview.bootmem.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.clcd]
type=Pl111
children=interrupt power_state
amba_id=1315089
clk_domain=board.clk_domain
enable_capture=true
eventq_index=0
interrupt=board.realview.clcd.interrupt
pio_addr=471793664
pio_latency=10000
pixel_clock=41667
power_model=
power_state=board.realview.clcd.power_state
sid=NullOpt
ssid=NullOpt
system=board
vnc=board.vncserver
dma=board.iobus.cpu_side_ports[1]
pio=board.iobus.mem_side_ports[16]

[board.realview.clcd.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=46
platform=board.realview

[board.realview.clcd.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.clock24MHz]
type=SrcClockDomain
clock=41667
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.realview.io_voltage

[board.realview.clock32KHz]
type=SrcClockDomain
clock=31250000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.realview.io_voltage

[board.realview.dcc]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null

[board.realview.dcc.osc_cpu]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=16667
max_freq=16667
min_freq=50000
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.dcc.osc_ddr]
type=RealViewOsc
dcc=0
device=8
eventq_index=0
freq=25000
max_freq=0
min_freq=0
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.dcc.osc_hsbm]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=25000
max_freq=25000
min_freq=50000
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.dcc.osc_pxl]
type=RealViewOsc
dcc=0
device=5
eventq_index=0
freq=42105
max_freq=6061
min_freq=42088
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.dcc.osc_smb]
type=RealViewOsc
dcc=0
device=6
eventq_index=0
freq=20000
max_freq=20000
min_freq=50000
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.dcc.osc_sys]
type=RealViewOsc
dcc=0
device=7
eventq_index=0
freq=16667
max_freq=16667
min_freq=50000
parent=board.realview.realview_io
position=0
site=1
voltage_domain=board.voltage_domain

[board.realview.el2_watchdog]
type=GenericWatchdog
children=power_state ws0 ws1
clk_domain=board.clk_domain
control_start=709099520
eventq_index=0
pio_latency=10000
power_model=
power_state=board.realview.el2_watchdog.power_state
refresh_start=709165056
system=board
system_counter=board.realview.sys_counter
ws0=board.realview.el2_watchdog.ws0
ws1=board.realview.el2_watchdog.ws1
pio=board.cache_hierarchy.membus.mem_side_ports[7]

[board.realview.el2_watchdog.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.el2_watchdog.ws0]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=59
platform=board.realview

[board.realview.el2_watchdog.ws1]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=60
platform=board.realview

[board.realview.energy_ctrl]
type=EnergyCtrl
children=power_state
clk_domain=board.clk_domain
dvfs_handler=board.dvfs_handler
eventq_index=0
pio_addr=268435456
pio_latency=100000
power_model=
power_state=board.realview.energy_ctrl.power_state
system=board
pio=board.iobus.mem_side_ports[8]

[board.realview.energy_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.flash0]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.flash0.power_state
range=134217728:201326592
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[5]

[board.realview.flash0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.flash1]
type=CfiMemory
children=power_state
bandwidth=73.000000
bank_width=4
blk_size=65536
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
device_id=0
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.flash1.power_state
range=201326592:268435456
vendor_id=0
writeable=true
port=board.iobus.mem_side_ports[0]

[board.realview.flash1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.generic_timer]
type=GenericTimer
children=int_el1_phys int_el1_virt int_el2_ns_phys int_el2_ns_virt int_el2_s_phys int_el2_s_virt int_el3_phys
cntfrq=25165824
counter=board.realview.sys_counter
eventq_index=0
int_el1_phys=board.realview.generic_timer.int_el1_phys
int_el1_virt=board.realview.generic_timer.int_el1_virt
int_el2_ns_phys=board.realview.generic_timer.int_el2_ns_phys
int_el2_ns_virt=board.realview.generic_timer.int_el2_ns_virt
int_el2_s_phys=board.realview.generic_timer.int_el2_s_phys
int_el2_s_virt=board.realview.generic_timer.int_el2_s_virt
int_el3_phys=board.realview.generic_timer.int_el3_phys
system=board

[board.realview.generic_timer.int_el1_phys]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=30
platform=board.realview

[board.realview.generic_timer.int_el1_virt]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=27
platform=board.realview

[board.realview.generic_timer.int_el2_ns_phys]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=26
platform=board.realview

[board.realview.generic_timer.int_el2_ns_virt]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=28
platform=board.realview

[board.realview.generic_timer.int_el2_s_phys]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=20
platform=board.realview

[board.realview.generic_timer.int_el2_s_virt]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=19
platform=board.realview

[board.realview.generic_timer.int_el3_phys]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_LOW
num=29
platform=board.realview

[board.realview.generic_timer_mem]
type=GenericTimerMem
children=frames0 frames1 power_state
clk_domain=board.clk_domain
cnt_control_base=709033984
cnt_ctl_base=713097216
cnt_read_base=713031680
counter=board.realview.sys_counter
eventq_index=0
frames=board.realview.generic_timer_mem.frames0 board.realview.generic_timer_mem.frames1
power_model=
power_state=board.realview.generic_timer_mem.power_state
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[6]

[board.realview.generic_timer_mem.frames0]
type=GenericTimerFrame
children=int_phys int_virt power_state
clk_domain=board.clk_domain
cnt_base=713162752
cnt_el0_base=18446744073709551615
counter=board.realview.sys_counter
eventq_index=0
int_phys=board.realview.generic_timer_mem.frames0.int_phys
int_virt=board.realview.generic_timer_mem.frames0.int_virt
power_model=
power_state=board.realview.generic_timer_mem.frames0.power_state
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[10]

[board.realview.generic_timer_mem.frames0.int_phys]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=57
platform=board.realview

[board.realview.generic_timer_mem.frames0.int_virt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=133
platform=board.realview

[board.realview.generic_timer_mem.frames0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.generic_timer_mem.frames1]
type=GenericTimerFrame
children=int_phys int_virt power_state
clk_domain=board.clk_domain
cnt_base=713228288
cnt_el0_base=18446744073709551615
counter=board.realview.sys_counter
eventq_index=0
int_phys=board.realview.generic_timer_mem.frames1.int_phys
int_virt=board.realview.generic_timer_mem.frames1.int_virt
power_model=
power_state=board.realview.generic_timer_mem.frames1.power_state
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[11]

[board.realview.generic_timer_mem.frames1.int_phys]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=58
platform=board.realview

[board.realview.generic_timer_mem.frames1.int_virt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=134
platform=board.realview

[board.realview.generic_timer_mem.frames1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.generic_timer_mem.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.gic]
type=Gicv3
children=maint_int power_state
clk_domain=board.clk_domain
cpu_max=256
dist_addr=788529152
dist_pio_delay=10000
eventq_index=0
gicc_iidr=0
gicd_iidr=0
gicd_pidr=0
gicv4=false
gicv_iidr=0
it_lines=1020
its=Null
maint_int=board.realview.gic.maint_int
platform=board.realview
power_model=
power_state=board.realview.gic.power_state
redist_addr=789577728
redist_pio_delay=10000
reserved_is_res0=true
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[12]

[board.realview.gic.maint_int]
type=ArmPPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=25
platform=board.realview

[board.realview.gic.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.io_voltage]
type=VoltageDomain
eventq_index=0
voltage=3.3

[board.realview.kmi0]
type=Pl050
children=interrupt power_state ps2
amba_id=1314896
clk_domain=board.clk_domain
eventq_index=0
int_delay=100000
interrupt=board.realview.kmi0.interrupt
pio_addr=470155264
pio_latency=100000
power_model=
power_state=board.realview.kmi0.power_state
ps2=board.realview.kmi0.ps2
system=board
pio=board.iobus.mem_side_ports[3]

[board.realview.kmi0.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=44
platform=board.realview

[board.realview.kmi0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.kmi0.ps2]
type=PS2Keyboard
eventq_index=0
vnc=board.vncserver

[board.realview.kmi1]
type=Pl050
children=interrupt power_state ps2
amba_id=1314896
clk_domain=board.clk_domain
eventq_index=0
int_delay=100000
interrupt=board.realview.kmi1.interrupt
pio_addr=470220800
pio_latency=100000
power_model=
power_state=board.realview.kmi1.power_state
ps2=board.realview.kmi1.ps2
system=board
pio=board.iobus.mem_side_ports[4]

[board.realview.kmi1.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=45
platform=board.realview

[board.realview.kmi1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.kmi1.ps2]
type=PS2TouchKit
eventq_index=0
vnc=board.vncserver

[board.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null

[board.realview.mcc.osc_clcd]
type=RealViewOsc
dcc=0
device=1
eventq_index=0
freq=42105
max_freq=15748
min_freq=42105
parent=board.realview.realview_io
position=0
site=0
voltage_domain=board.voltage_domain

[board.realview.mcc.osc_mcc]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=20000
max_freq=16667
min_freq=40000
parent=board.realview.realview_io
position=0
site=0
voltage_domain=board.voltage_domain

[board.realview.mcc.osc_peripheral]
type=RealViewOsc
dcc=0
device=2
eventq_index=0
freq=41667
max_freq=0
min_freq=0
parent=board.realview.realview_io
position=0
site=0
voltage_domain=board.voltage_domain

[board.realview.mcc.osc_system_bus]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=41667
max_freq=4348
min_freq=500000
parent=board.realview.realview_io
position=0
site=0
voltage_domain=board.voltage_domain

[board.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=board.realview.realview_io
position=0
site=0
system=board

[board.realview.non_trusted_sram]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.non_trusted_sram.power_state
range=771751936:771784704
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[4]

[board.realview.non_trusted_sram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.pci_host]
type=GenericArmPciHost
children=power_state
clk_domain=board.clk_domain
conf_base=1073741824
conf_device_bits=12
conf_size=268435456
eventq_index=0
int_base=100
int_count=4
int_policy=ARM_PCI_INT_DEV
pci_dma_base=0
pci_mem_base=274877906944
pci_pio_base=1342177280
platform=board.realview
power_model=
power_state=board.realview.pci_host.power_state
system=board
pio=board.iobus.mem_side_ports[7]

[board.realview.pci_host.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.pwr_ctrl]
type=FVPBasePwrCtrl
children=power_state
clk_domain=board.clk_domain
eventq_index=0
pio_addr=470810624
pio_latency=100000
power_model=
power_state=board.realview.pwr_ctrl.power_state
system=board
pio=board.iobus.mem_side_ports[9]

[board.realview.pwr_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.realview_io]
type=RealViewCtrl
children=power_state
clk_domain=board.clk_domain
eventq_index=0
idreg=806359296
pio_addr=469827584
pio_latency=100000
power_model=
power_state=board.realview.realview_io.power_state
proc_id0=335544320
proc_id1=335544320
system=board
pio=board.iobus.mem_side_ports[2]

[board.realview.realview_io.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.rtc]
type=PL031
children=interrupt power_state
amba_id=266289
clk_domain=board.clk_domain
eventq_index=0
int_delay=100000
interrupt=board.realview.rtc.interrupt
pio_addr=471269376
pio_latency=100000
power_model=
power_state=board.realview.rtc.power_state
system=board
time=Thu Jan  1 00:00:00 2009
pio=board.iobus.mem_side_ports[6]

[board.realview.rtc.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=36
platform=board.realview

[board.realview.rtc.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.sp810_fake]
type=AmbaFake
children=power_state
amba_id=0
clk_domain=board.clk_domain
eventq_index=0
ignore_access=true
pio_addr=469893120
pio_latency=100000
power_model=
power_state=board.realview.sp810_fake.power_state
system=board
pio=board.iobus.mem_side_ports[17]

[board.realview.sp810_fake.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.sys_counter]
type=SystemCounter
eventq_index=0
freqs=25165824

[board.realview.system_watchdog]
type=Sp805
children=interrupt power_state
amba_id=1316869
clk_domain=board.realview.dcc.osc_sys
eventq_index=0
int_delay=100000
interrupt=board.realview.system_watchdog.interrupt
pio_addr=721813504
pio_latency=100000
power_model=
power_state=board.realview.system_watchdog.power_state
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[9]

[board.realview.system_watchdog.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=130
platform=board.realview

[board.realview.system_watchdog.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.trusted_dram]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.trusted_dram.power_state
range=100663296:134217728
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[3]

[board.realview.trusted_dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.trusted_sram]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.trusted_sram.power_state
range=67108864:67371008
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[2]

[board.realview.trusted_sram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.trusted_watchdog]
type=Sp805
children=interrupt power_state
amba_id=1316869
clk_domain=board.clk_domain
eventq_index=0
int_delay=100000
interrupt=board.realview.trusted_watchdog.interrupt
pio_addr=709427200
pio_latency=100000
power_model=
power_state=board.realview.trusted_watchdog.power_state
system=board
pio=board.cache_hierarchy.membus.mem_side_ports[8]

[board.realview.trusted_watchdog.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=56
platform=board.realview

[board.realview.trusted_watchdog.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.uart0]
type=Pl011
children=interrupt power_state
clk_domain=board.clk_domain
device=board.terminal
end_on_eot=false
eventq_index=0
int_delay=100000
interrupt=board.realview.uart0.interrupt
pio_addr=470351872
pio_latency=100000
platform=board.realview
power_model=
power_state=board.realview.uart0.power_state
system=board
pio=board.iobus.mem_side_ports[12]

[board.realview.uart0.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=37
platform=board.realview

[board.realview.uart0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.uart1]
type=Pl011
children=device interrupt power_state
clk_domain=board.clk_domain
device=board.realview.uart1.device
end_on_eot=false
eventq_index=0
int_delay=100000
interrupt=board.realview.uart1.interrupt
pio_addr=470417408
pio_latency=100000
platform=board.realview
power_model=
power_state=board.realview.uart1.power_state
system=board
pio=board.iobus.mem_side_ports[13]

[board.realview.uart1.device]
type=Terminal
eventq_index=0
number=0
outfile=file
port=#3456

[board.realview.uart1.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=38
platform=board.realview

[board.realview.uart1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.uart2]
type=Pl011
children=device interrupt power_state
clk_domain=board.clk_domain
device=board.realview.uart2.device
end_on_eot=false
eventq_index=0
int_delay=100000
interrupt=board.realview.uart2.interrupt
pio_addr=470482944
pio_latency=100000
platform=board.realview
power_model=
power_state=board.realview.uart2.power_state
system=board
pio=board.iobus.mem_side_ports[14]

[board.realview.uart2.device]
type=Terminal
eventq_index=0
number=0
outfile=file
port=#3456

[board.realview.uart2.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=39
platform=board.realview

[board.realview.uart2.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.uart3]
type=Pl011
children=device interrupt power_state
clk_domain=board.clk_domain
device=board.realview.uart3.device
end_on_eot=false
eventq_index=0
int_delay=100000
interrupt=board.realview.uart3.interrupt
pio_addr=470548480
pio_latency=100000
platform=board.realview
power_model=
power_state=board.realview.uart3.power_state
system=board
pio=board.iobus.mem_side_ports[15]

[board.realview.uart3.device]
type=Terminal
eventq_index=0
number=0
outfile=file
port=#3456

[board.realview.uart3.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=40
platform=board.realview

[board.realview.uart3.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.vio0]
type=MmioVirtIO
children=interrupt power_state vio
clk_domain=board.clk_domain
eventq_index=0
interrupt=board.realview.vio0.interrupt
pio_addr=471007232
pio_latency=100000
pio_size=4096
power_model=
power_state=board.realview.vio0.power_state
system=board
vio=board.realview.vio0.vio
pio=board.iobus.mem_side_ports[10]

[board.realview.vio0.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=74
platform=board.realview

[board.realview.vio0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.vio0.vio]
type=VirtIODummyDevice
byte_order=little
eventq_index=0
subsystem=0
system=board

[board.realview.vio1]
type=MmioVirtIO
children=interrupt power_state vio
clk_domain=board.clk_domain
eventq_index=0
interrupt=board.realview.vio1.interrupt
pio_addr=471072768
pio_latency=100000
pio_size=4096
power_model=
power_state=board.realview.vio1.power_state
system=board
vio=board.realview.vio1.vio
pio=board.iobus.mem_side_ports[11]

[board.realview.vio1.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=75
platform=board.realview

[board.realview.vio1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.vio1.vio]
type=VirtIODummyDevice
byte_order=little
eventq_index=0
subsystem=0
system=board

[board.realview.vram]
type=SimpleMemory
children=power_state
bandwidth=73.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
power_model=
power_state=board.realview.vram.power_state
range=402653184:436207616
writeable=true
port=board.iobus.mem_side_ports[1]

[board.realview.vram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.realview.watchdog]
type=Sp805
children=interrupt power_state
amba_id=1316869
clk_domain=board.realview.clock32KHz
eventq_index=0
int_delay=100000
interrupt=board.realview.watchdog.interrupt
pio_addr=470745088
pio_latency=100000
power_model=
power_state=board.realview.watchdog.power_state
system=board
pio=board.iobus.mem_side_ports[5]

[board.realview.watchdog.interrupt]
type=ArmSPI
eventq_index=0
int_type=IRQ_TYPE_LEVEL_HIGH
num=32
platform=board.realview

[board.realview.watchdog.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.release]
type=ArmRelease
eventq_index=0
extensions=LPAE VIRTUALIZATION SECURITY FEAT_AES FEAT_PMULL FEAT_SHA1 FEAT_SHA256 FEAT_CRC32 FEAT_LSE FEAT_PAN FEAT_HPDS FEAT_VMID16 FEAT_RDM FEAT_UAO FEAT_LVA FEAT_LPA FEAT_SVE FEAT_F32MM FEAT_F64MM FEAT_I8MM FEAT_DOTPROD FEAT_FP16 FEAT_FCMA FEAT_JSCVT FEAT_PAuth FEAT_SEL2 FEAT_TLBIOS FEAT_TLBIRANGE FEAT_FLAGM FEAT_IDST FEAT_TTST FEAT_FLAGM2 FEAT_EVT FEAT_FGT FEAT_HCX FEAT_XS FEAT_SME

[board.terminal]
type=Terminal
eventq_index=0
number=0
outfile=file
port=#3456

[board.vncserver]
type=VncServer
eventq_index=0
frame_capture=false
img_format=Auto
number=0
port=#5900

[board.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[board.workload]
type=ArmFsLinux
addr_check=true
boot_loader=gem5/arm64-bootloader-foundation
command_line=console=ttyAMA0 lpj=19988480 norandmaps root=/dev/vda2 disk_device=/dev/vda rw mem=1073741824
cpu_release_addr=2281701368
dtb_addr=2281701376
dtb_filename=FS_mode/device.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
extras=
extras_addrs=
initrd_addr=2283798528
initrd_filename=
load_addr_mask=0
load_addr_offset=2147483648
machine_type=DTOnly
object_file=gem5/arm64-linux-kernel-6.8.12
on_oops=DumpDmesgAndExit
on_panic=DumpDmesgAndExit
panic_on_oops=false
panic_on_panic=false
remote_gdb_port=#7000
wait_for_remote_gdb=false

[root]
type=Root
children=board
eventq_index=0
full_system=true
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000