---------- Begin Simulation Statistics ----------
simSeconds 0.001000 # Number of seconds simulated (Second)
simTicks 1000000000 # Number of ticks simulated (Tick)
finalTick 1000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 1.86 # Real time elapsed on the host (Second)
hostTickRate 538698483 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 1570448 # Number of bytes of host memory used (Byte)
board.cache_hierarchy.dptw_caches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches2.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches2.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches2.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches2.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches2.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches2.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches2.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches3.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches3.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches3.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches3.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches3.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches3.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches3.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches3.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches4.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches4.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches4.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches4.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches4.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches4.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches4.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches4.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches5.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches5.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches5.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches5.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches5.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches5.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches5.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches5.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches2.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches2.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches2.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches2.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches2.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches2.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches2.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches3.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches3.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches3.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches3.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches3.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches3.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches3.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches3.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches4.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches4.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches4.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches4.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches4.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches4.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches4.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches4.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches5.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches5.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches5.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches5.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches5.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches5.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches5.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches5.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.demandHits::processor.cores0.generator 132626 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.demandHits::total 132626 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::processor.cores0.generator 132626 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::total 132626 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::processor.cores0.generator 1584 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::total 1584 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::processor.cores0.generator 1584 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::total 1584 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.demandMissLatency::processor.cores0.generator 38929711 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMissLatency::total 38929711 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::processor.cores0.generator 38929711 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::total 38929711 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandAccesses::processor.cores0.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::processor.cores0.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandMissRate::processor.cores0.generator 0.011802 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMissRate::total 0.011802 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::processor.cores0.generator 0.011802 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::total 0.011802 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::processor.cores0.generator 24576.837753 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::total 24576.837753 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::processor.cores0.generator 24576.837753 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::total 24576.837753 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.demandMshrHits::processor.cores0.generator 1319 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.demandMshrHits::total 1319 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.overallMshrHits::processor.cores0.generator 1319 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.overallMshrHits::total 1319 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::processor.cores0.generator 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::total 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::cache_hierarchy.l1dcaches0.prefetcher 16516 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::processor.cores0.generator 265 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::total 16781 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::processor.cores0.generator 11255373 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::total 11255373 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 487681138 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::processor.cores0.generator 11255373 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::total 498936511 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::processor.cores0.generator 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::total 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::processor.cores0.generator 0.001975 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::total 0.125035 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::processor.cores0.generator 42473.105660 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::total 42473.105660 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 29527.799588 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::processor.cores0.generator 42473.105660 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::total 29732.227579 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.replacements 16524 # number of replacements (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches0.prefetcher 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::total 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 487681138 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::total 487681138 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 29527.799588 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::total 29527.799588 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.hits::processor.cores0.generator 132626 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.hits::total 132626 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::processor.cores0.generator 1584 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::total 1584 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::processor.cores0.generator 38929711 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::total 38929711 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::processor.cores0.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::processor.cores0.generator 0.011802 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::total 0.011802 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::processor.cores0.generator 24576.837753 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::total 24576.837753 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.mshrHits::processor.cores0.generator 1319 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrHits::total 1319 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::processor.cores0.generator 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::total 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::processor.cores0.generator 11255373 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::total 11255373 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::processor.cores0.generator 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::total 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::processor.cores0.generator 42473.105660 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::total 42473.105660 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.prefetcher.demandMshrMisses 265 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIssued 64480 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUseful 16512 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.accuracy 0.256079 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.coverage 0.984205 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInCache 47701 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInMSHR 263 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfLate 47964 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIdentified 64480 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfSpanPage 2620 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulSpanPage 2620 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.tags.tagsInUse 254.102754 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches0.tags.totalRefs 149406 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.sampledRefs 16780 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.avgRefs 8.903814 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches0.tags.warmupTick 31635 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches0.tags.occupancies::cache_hierarchy.l1dcaches0.prefetcher 250.095497 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupancies::processor.cores0.generator 4.007258 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::cache_hierarchy.l1dcaches0.prefetcher 0.976936 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::processor.cores0.generator 0.015653 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::total 0.992589 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1022 252 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1024 4 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1022::0 165 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1022::1 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::0 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1022 0.984375 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1024 0.015625 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.tagAccesses 1090460 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.dataAccesses 1090460 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.demandHits::processor.cores1.generator 132850 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.demandHits::total 132850 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::processor.cores1.generator 132850 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::total 132850 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::processor.cores1.generator 1360 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::total 1360 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::processor.cores1.generator 1360 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::total 1360 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.demandMissLatency::processor.cores1.generator 29672585 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMissLatency::total 29672585 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::processor.cores1.generator 29672585 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::total 29672585 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandAccesses::processor.cores1.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::processor.cores1.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandMissRate::processor.cores1.generator 0.010133 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMissRate::total 0.010133 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::processor.cores1.generator 0.010133 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::total 0.010133 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::processor.cores1.generator 21818.077206 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::total 21818.077206 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::processor.cores1.generator 21818.077206 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::total 21818.077206 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.demandMshrHits::processor.cores1.generator 1095 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.demandMshrHits::total 1095 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.overallMshrHits::processor.cores1.generator 1095 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.overallMshrHits::total 1095 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::processor.cores1.generator 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::total 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::cache_hierarchy.l1dcaches1.prefetcher 16516 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::processor.cores1.generator 265 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::total 16781 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::processor.cores1.generator 9717579 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::total 9717579 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 460063732 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::processor.cores1.generator 9717579 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::total 469781311 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::processor.cores1.generator 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::total 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::processor.cores1.generator 0.001975 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::total 0.125035 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::processor.cores1.generator 36670.109434 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::total 36670.109434 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 27855.638896 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::processor.cores1.generator 36670.109434 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::total 27994.834098 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.replacements 16524 # number of replacements (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches1.prefetcher 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::total 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 460063732 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::total 460063732 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 27855.638896 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::total 27855.638896 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.hits::processor.cores1.generator 132850 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.hits::total 132850 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::processor.cores1.generator 1360 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::total 1360 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::processor.cores1.generator 29672585 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::total 29672585 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::processor.cores1.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::processor.cores1.generator 0.010133 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::total 0.010133 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::processor.cores1.generator 21818.077206 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::total 21818.077206 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.mshrHits::processor.cores1.generator 1095 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrHits::total 1095 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::processor.cores1.generator 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::total 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::processor.cores1.generator 9717579 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::total 9717579 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::processor.cores1.generator 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::total 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::processor.cores1.generator 36670.109434 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::total 36670.109434 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.prefetcher.demandMshrMisses 265 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIssued 64480 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUseful 16512 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.accuracy 0.256079 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.coverage 0.984205 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInCache 47701 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInMSHR 263 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfLate 47964 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIdentified 64480 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfSpanPage 2620 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulSpanPage 2620 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.tags.tagsInUse 254.103086 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches1.tags.totalRefs 149630 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.sampledRefs 16780 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.avgRefs 8.917163 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches1.tags.warmupTick 33633 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches1.tags.occupancies::cache_hierarchy.l1dcaches1.prefetcher 250.095791 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupancies::processor.cores1.generator 4.007295 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::cache_hierarchy.l1dcaches1.prefetcher 0.976937 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::processor.cores1.generator 0.015653 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::total 0.992590 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1022 252 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1024 4 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1022::0 165 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1022::1 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1024::0 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1022 0.984375 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1024 0.015625 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.tagAccesses 1090460 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.dataAccesses 1090460 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.demandHits::processor.cores2.generator 132650 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches2.demandHits::total 132650 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches2.overallHits::processor.cores2.generator 132650 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches2.overallHits::total 132650 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches2.demandMisses::processor.cores2.generator 1560 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches2.demandMisses::total 1560 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches2.overallMisses::processor.cores2.generator 1560 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches2.overallMisses::total 1560 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches2.demandMissLatency::processor.cores2.generator 32871782 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMissLatency::total 32871782 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMissLatency::processor.cores2.generator 32871782 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMissLatency::total 32871782 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandAccesses::processor.cores2.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.overallAccesses::processor.cores2.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.demandMissRate::processor.cores2.generator 0.011624 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandMissRate::total 0.011624 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMissRate::processor.cores2.generator 0.011624 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMissRate::total 0.011624 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandAvgMissLatency::processor.cores2.generator 21071.655128 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches2.demandAvgMissLatency::total 21071.655128 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMissLatency::processor.cores2.generator 21071.655128 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMissLatency::total 21071.655128 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches2.demandMshrHits::processor.cores2.generator 1295 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.demandMshrHits::total 1295 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.overallMshrHits::processor.cores2.generator 1295 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.overallMshrHits::total 1295 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMisses::processor.cores2.generator 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMisses::total 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::cache_hierarchy.l1dcaches2.prefetcher 16516 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::processor.cores2.generator 265 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::total 16781 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMissLatency::processor.cores2.generator 10250046 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMshrMissLatency::total 10250046 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 432916377 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::processor.cores2.generator 10250046 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::total 443166423 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMshrMissRate::processor.cores2.generator 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandMshrMissRate::total 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::cache_hierarchy.l1dcaches2.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::processor.cores2.generator 0.001975 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::total 0.125035 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandAvgMshrMissLatency::processor.cores2.generator 38679.418868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.demandAvgMshrMissLatency::total 38679.418868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 26211.938544 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::processor.cores2.generator 38679.418868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::total 26408.820869 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.replacements 16524 # number of replacements (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches2.prefetcher 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMisses::total 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 432916377 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissLatency::total 432916377 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches2.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 26211.938544 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.HardPFReq.avgMshrMissLatency::total 26211.938544 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.hits::processor.cores2.generator 132650 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.hits::total 132650 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.misses::processor.cores2.generator 1560 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.misses::total 1560 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.missLatency::processor.cores2.generator 32871782 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.missLatency::total 32871782 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.accesses::processor.cores2.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.missRate::processor.cores2.generator 0.011624 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.missRate::total 0.011624 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.avgMissLatency::processor.cores2.generator 21071.655128 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.avgMissLatency::total 21071.655128 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.mshrHits::processor.cores2.generator 1295 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrHits::total 1295 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMisses::processor.cores2.generator 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMisses::total 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissLatency::processor.cores2.generator 10250046 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissLatency::total 10250046 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissRate::processor.cores2.generator 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissRate::total 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.avgMshrMissLatency::processor.cores2.generator 38679.418868 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.avgMshrMissLatency::total 38679.418868 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.prefetcher.demandMshrMisses 265 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfIssued 64480 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUseful 16512 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.accuracy 0.256079 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.coverage 0.984205 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInCache 47652 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInMSHR 312 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfLate 47964 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfIdentified 64480 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfSpanPage 2620 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUsefulSpanPage 2620 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.tags.tagsInUse 254.103473 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches2.tags.totalRefs 149430 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches2.tags.sampledRefs 16780 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches2.tags.avgRefs 8.905244 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches2.tags.warmupTick 35631 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches2.tags.occupancies::cache_hierarchy.l1dcaches2.prefetcher 250.096186 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches2.tags.occupancies::processor.cores2.generator 4.007287 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::cache_hierarchy.l1dcaches2.prefetcher 0.976938 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::processor.cores2.generator 0.015653 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::total 0.992592 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.occupanciesTaskId::1022 252 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches2.tags.occupanciesTaskId::1024 4 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1022::0 165 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1022::1 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1024::0 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ratioOccsTaskId::1022 0.984375 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches2.tags.ratioOccsTaskId::1024 0.015625 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches2.tags.tagAccesses 1090460 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches2.tags.dataAccesses 1090460 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.demandHits::processor.cores3.generator 132625 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches3.demandHits::total 132625 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches3.overallHits::processor.cores3.generator 132625 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches3.overallHits::total 132625 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches3.demandMisses::processor.cores3.generator 1585 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches3.demandMisses::total 1585 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches3.overallMisses::processor.cores3.generator 1585 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches3.overallMisses::total 1585 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches3.demandMissLatency::processor.cores3.generator 36121505 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMissLatency::total 36121505 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMissLatency::processor.cores3.generator 36121505 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMissLatency::total 36121505 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandAccesses::processor.cores3.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.overallAccesses::processor.cores3.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.demandMissRate::processor.cores3.generator 0.011810 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandMissRate::total 0.011810 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMissRate::processor.cores3.generator 0.011810 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMissRate::total 0.011810 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandAvgMissLatency::processor.cores3.generator 22789.593060 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches3.demandAvgMissLatency::total 22789.593060 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMissLatency::processor.cores3.generator 22789.593060 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMissLatency::total 22789.593060 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches3.demandMshrHits::processor.cores3.generator 1320 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.demandMshrHits::total 1320 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.overallMshrHits::processor.cores3.generator 1320 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.overallMshrHits::total 1320 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMisses::processor.cores3.generator 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMisses::total 265 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::cache_hierarchy.l1dcaches3.prefetcher 16516 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::processor.cores3.generator 265 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::total 16781 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMissLatency::processor.cores3.generator 10792170 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMshrMissLatency::total 10792170 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 405443652 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::processor.cores3.generator 10792170 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::total 416235822 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMshrMissRate::processor.cores3.generator 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandMshrMissRate::total 0.001975 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::cache_hierarchy.l1dcaches3.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::processor.cores3.generator 0.001975 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::total 0.125035 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandAvgMshrMissLatency::processor.cores3.generator 40725.169811 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.demandAvgMshrMissLatency::total 40725.169811 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 24548.537903 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::processor.cores3.generator 40725.169811 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::total 24803.993922 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.replacements 16524 # number of replacements (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches3.prefetcher 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMisses::total 16516 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 405443652 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissLatency::total 405443652 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches3.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 24548.537903 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.HardPFReq.avgMshrMissLatency::total 24548.537903 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.hits::processor.cores3.generator 132625 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.hits::total 132625 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.misses::processor.cores3.generator 1585 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.misses::total 1585 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.missLatency::processor.cores3.generator 36121505 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.missLatency::total 36121505 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.accesses::processor.cores3.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.missRate::processor.cores3.generator 0.011810 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.missRate::total 0.011810 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.avgMissLatency::processor.cores3.generator 22789.593060 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.avgMissLatency::total 22789.593060 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.mshrHits::processor.cores3.generator 1320 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrHits::total 1320 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMisses::processor.cores3.generator 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMisses::total 265 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissLatency::processor.cores3.generator 10792170 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissLatency::total 10792170 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissRate::processor.cores3.generator 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissRate::total 0.001975 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.avgMshrMissLatency::processor.cores3.generator 40725.169811 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.avgMshrMissLatency::total 40725.169811 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.prefetcher.demandMshrMisses 265 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfIssued 64480 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUseful 16512 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.accuracy 0.256079 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.coverage 0.984205 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInCache 47620 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInMSHR 344 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfLate 47964 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfIdentified 64480 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfSpanPage 2620 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUsefulSpanPage 2620 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.tags.tagsInUse 254.103877 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches3.tags.totalRefs 149405 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches3.tags.sampledRefs 16780 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches3.tags.avgRefs 8.903754 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches3.tags.warmupTick 37296 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches3.tags.occupancies::cache_hierarchy.l1dcaches3.prefetcher 250.096597 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches3.tags.occupancies::processor.cores3.generator 4.007280 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::cache_hierarchy.l1dcaches3.prefetcher 0.976940 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::processor.cores3.generator 0.015653 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::total 0.992593 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.occupanciesTaskId::1022 252 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches3.tags.occupanciesTaskId::1024 4 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1022::0 165 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1022::1 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1024::0 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ratioOccsTaskId::1022 0.984375 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches3.tags.ratioOccsTaskId::1024 0.015625 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches3.tags.tagAccesses 1090460 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches3.tags.dataAccesses 1090460 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.demandHits::processor.cores4.generator 16929 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches4.demandHits::total 16929 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches4.overallHits::processor.cores4.generator 16929 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches4.overallHits::total 16929 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches4.demandMisses::processor.cores4.generator 117281 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches4.demandMisses::total 117281 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches4.overallMisses::processor.cores4.generator 117281 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches4.overallMisses::total 117281 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches4.demandMissLatency::processor.cores4.generator 3176862752 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMissLatency::total 3176862752 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMissLatency::processor.cores4.generator 3176862752 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMissLatency::total 3176862752 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandAccesses::processor.cores4.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.overallAccesses::processor.cores4.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.demandMissRate::processor.cores4.generator 0.873862 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandMissRate::total 0.873862 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMissRate::processor.cores4.generator 0.873862 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMissRate::total 0.873862 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandAvgMissLatency::processor.cores4.generator 27087.616511 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches4.demandAvgMissLatency::total 27087.616511 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMissLatency::processor.cores4.generator 27087.616511 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMissLatency::total 27087.616511 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches4.demandMshrHits::processor.cores4.generator 202 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.demandMshrHits::total 202 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.overallMshrHits::processor.cores4.generator 202 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.overallMshrHits::total 202 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMisses::processor.cores4.generator 117079 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMisses::total 117079 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.overallMshrMisses::processor.cores4.generator 117079 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.overallMshrMisses::total 117079 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMissLatency::processor.cores4.generator 3135498240 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMshrMissLatency::total 3135498240 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMshrMissLatency::processor.cores4.generator 3135498240 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMshrMissLatency::total 3135498240 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMshrMissRate::processor.cores4.generator 0.872357 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandMshrMissRate::total 0.872357 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMshrMissRate::processor.cores4.generator 0.872357 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMshrMissRate::total 0.872357 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandAvgMshrMissLatency::processor.cores4.generator 26781.047327 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.demandAvgMshrMissLatency::total 26781.047327 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMshrMissLatency::processor.cores4.generator 26781.047327 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMshrMissLatency::total 26781.047327 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.replacements 116820 # number of replacements (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.hits::processor.cores4.generator 16929 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.hits::total 16929 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.misses::processor.cores4.generator 117281 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.misses::total 117281 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.missLatency::processor.cores4.generator 3176862752 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.missLatency::total 3176862752 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.accesses::processor.cores4.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.missRate::processor.cores4.generator 0.873862 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.missRate::total 0.873862 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.avgMissLatency::processor.cores4.generator 27087.616511 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.avgMissLatency::total 27087.616511 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.mshrHits::processor.cores4.generator 202 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrHits::total 202 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMisses::processor.cores4.generator 117079 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMisses::total 117079 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissLatency::processor.cores4.generator 3135498240 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissLatency::total 3135498240 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissRate::processor.cores4.generator 0.872357 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissRate::total 0.872357 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.avgMshrMissLatency::processor.cores4.generator 26781.047327 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.avgMshrMissLatency::total 26781.047327 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.prefetcher.demandMshrMisses 117079 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.tags.tagsInUse 255.709879 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches4.tags.totalRefs 134005 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches4.tags.sampledRefs 117076 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches4.tags.avgRefs 1.144598 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches4.tags.warmupTick 39294 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches4.tags.occupancies::processor.cores4.generator 255.709879 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches4.tags.avgOccs::processor.cores4.generator 0.998867 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches4.tags.avgOccs::total 0.998867 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches4.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches4.tags.ageTaskId_1024::0 256 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches4.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches4.tags.tagAccesses 1190756 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches4.tags.dataAccesses 1190756 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.demandHits::processor.cores5.generator 16932 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches5.demandHits::total 16932 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches5.overallHits::processor.cores5.generator 16932 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches5.overallHits::total 16932 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches5.demandMisses::processor.cores5.generator 117278 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches5.demandMisses::total 117278 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches5.overallMisses::processor.cores5.generator 117278 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches5.overallMisses::total 117278 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches5.demandMissLatency::processor.cores5.generator 3179719380 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMissLatency::total 3179719380 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMissLatency::processor.cores5.generator 3179719380 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMissLatency::total 3179719380 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandAccesses::processor.cores5.generator 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.demandAccesses::total 134210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.overallAccesses::processor.cores5.generator 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.overallAccesses::total 134210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.demandMissRate::processor.cores5.generator 0.873840 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandMissRate::total 0.873840 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMissRate::processor.cores5.generator 0.873840 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMissRate::total 0.873840 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandAvgMissLatency::processor.cores5.generator 27112.667167 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches5.demandAvgMissLatency::total 27112.667167 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMissLatency::processor.cores5.generator 27112.667167 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMissLatency::total 27112.667167 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches5.demandMshrHits::processor.cores5.generator 200 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.demandMshrHits::total 200 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.overallMshrHits::processor.cores5.generator 200 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.overallMshrHits::total 200 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMisses::processor.cores5.generator 117078 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMisses::total 117078 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.overallMshrMisses::processor.cores5.generator 117078 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.overallMshrMisses::total 117078 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMissLatency::processor.cores5.generator 3138347043 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMshrMissLatency::total 3138347043 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMshrMissLatency::processor.cores5.generator 3138347043 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMshrMissLatency::total 3138347043 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMshrMissRate::processor.cores5.generator 0.872349 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandMshrMissRate::total 0.872349 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMshrMissRate::processor.cores5.generator 0.872349 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMshrMissRate::total 0.872349 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandAvgMshrMissLatency::processor.cores5.generator 26805.608594 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.demandAvgMshrMissLatency::total 26805.608594 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMshrMissLatency::processor.cores5.generator 26805.608594 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMshrMissLatency::total 26805.608594 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.replacements 116819 # number of replacements (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.hits::processor.cores5.generator 16932 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.hits::total 16932 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.misses::processor.cores5.generator 117278 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.misses::total 117278 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.missLatency::processor.cores5.generator 3179719380 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.missLatency::total 3179719380 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.accesses::processor.cores5.generator 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.accesses::total 134210 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.missRate::processor.cores5.generator 0.873840 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.missRate::total 0.873840 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.avgMissLatency::processor.cores5.generator 27112.667167 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.avgMissLatency::total 27112.667167 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.mshrHits::processor.cores5.generator 200 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrHits::total 200 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMisses::processor.cores5.generator 117078 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMisses::total 117078 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissLatency::processor.cores5.generator 3138347043 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissLatency::total 3138347043 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissRate::processor.cores5.generator 0.872349 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissRate::total 0.872349 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.avgMshrMissLatency::processor.cores5.generator 26805.608594 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.avgMshrMissLatency::total 26805.608594 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.prefetcher.demandMshrMisses 117078 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.tags.tagsInUse 255.709754 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches5.tags.totalRefs 134007 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches5.tags.sampledRefs 117075 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches5.tags.avgRefs 1.144625 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches5.tags.warmupTick 41292 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches5.tags.occupancies::processor.cores5.generator 255.709754 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches5.tags.avgOccs::processor.cores5.generator 0.998866 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches5.tags.avgOccs::total 0.998866 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches5.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches5.tags.ageTaskId_1024::0 256 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches5.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches5.tags.tagAccesses 1190755 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches5.tags.dataAccesses 1190755 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches1.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches2.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches2.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches2.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches2.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches2.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches2.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches2.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches2.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches2.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches3.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches3.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches3.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches3.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches3.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches3.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches3.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches3.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches3.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches3.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches4.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches4.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches4.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches4.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches4.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches4.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches4.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches4.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches4.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches4.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches5.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches5.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches5.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches5.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches5.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches5.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches5.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches5.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches5.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches5.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 301272 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 299733 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 301278 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.module.port 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::total 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.module.port 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::total 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches2.mem_side_port::board.memory.module.port 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches2.mem_side_port::total 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches3.mem_side_port::board.memory.module.port 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches3.mem_side_port::total 50085 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches4.mem_side_port::board.memory.module.port 350974 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches4.mem_side_port::total 350974 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches5.mem_side_port::board.memory.module.port 350969 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches5.mem_side_port::total 350969 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 902283 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.module.port 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::total 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.module.port 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::total 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches2.mem_side_port::board.memory.module.port 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches2.mem_side_port::total 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches3.mem_side_port::board.memory.module.port 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches3.mem_side_port::total 1073920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches4.mem_side_port::board.memory.module.port 7492928 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches4.mem_side_port::total 7492928 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches5.mem_side_port::board.memory.module.port 7492800 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches5.mem_side_port::total 7492800 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 19281408 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 497026 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0.909995 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0.781637 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 176211 35.45% 35.45% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 189339 38.09% 73.55% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 131476 26.45% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::5 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::6 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::7 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::8 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::9 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::10 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::11 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::12 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::13 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::14 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::15 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::16 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::17 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::18 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::19 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::20 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::21 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::22 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::23 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::24 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 2 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 497026 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 298188585 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.3 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer10.occupancy 16427620 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer10.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer14.occupancy 16427620 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer14.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer18.occupancy 114618383 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer18.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 16427620 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer22.occupancy 114616425 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer22.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer6.occupancy 16427620 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer6.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 796759 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 305658 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 314890 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.module.bytesRead::cache_hierarchy.l1dcaches0.prefetcher 1057024 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::cache_hierarchy.l1dcaches1.prefetcher 1057024 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::cache_hierarchy.l1dcaches2.prefetcher 1057024 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::cache_hierarchy.l1dcaches3.prefetcher 1057024 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores0.generator 16960 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores1.generator 16960 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores2.generator 16960 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores3.generator 16960 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores4.generator 7492992 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores5.generator 7492864 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::total 19281792 # Number of bytes read from this memory (Byte)
board.memory.module.numReads::cache_hierarchy.l1dcaches0.prefetcher 16516 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::cache_hierarchy.l1dcaches1.prefetcher 16516 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::cache_hierarchy.l1dcaches2.prefetcher 16516 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::cache_hierarchy.l1dcaches3.prefetcher 16516 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores0.generator 265 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores1.generator 265 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores2.generator 265 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores3.generator 265 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores4.generator 117078 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores5.generator 117076 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::total 301278 # Number of read requests responded to by this memory (Count)
board.memory.module.bwRead::cache_hierarchy.l1dcaches0.prefetcher 1057024000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::cache_hierarchy.l1dcaches1.prefetcher 1057024000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::cache_hierarchy.l1dcaches2.prefetcher 1057024000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::cache_hierarchy.l1dcaches3.prefetcher 1057024000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores0.generator 16960000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores1.generator 16960000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores2.generator 16960000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores3.generator 16960000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores4.generator 7492992000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores5.generator 7492864000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::total 19281792000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l1dcaches0.prefetcher 1057024000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l1dcaches1.prefetcher 1057024000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l1dcaches2.prefetcher 1057024000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l1dcaches3.prefetcher 1057024000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores0.generator 16960000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores1.generator 16960000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores2.generator 16960000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores3.generator 16960000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores4.generator 7492992000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores5.generator 7492864000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::total 19281792000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores0.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores0.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores0.generator.numRetries 0 # Number of retries (Count)
board.processor.cores0.generator.retryTicks 0 # Time spent waiting due to back-pressure (Tick)
board.processor.cores0.generator.bytesRead 1073680 # Number of bytes read (Byte)
board.processor.cores0.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores0.generator.totalReadLatency 105112156 # Total latency of read requests (Tick)
board.processor.cores0.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores0.generator.totalReads 134210 # Total num of reads (Count)
board.processor.cores0.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores0.generator.avgReadLatency 783.191685 # Avg latency of read requests ((Tick/Count))
board.processor.cores0.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores0.generator.readBW 1073680000 # Read bandwidth ((Byte/Second))
board.processor.cores0.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores0.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores1.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores1.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores1.generator.numRetries 0 # Number of retries (Count)
board.processor.cores1.generator.retryTicks 0 # Time spent waiting due to back-pressure (Tick)
board.processor.cores1.generator.bytesRead 1073680 # Number of bytes read (Byte)
board.processor.cores1.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores1.generator.totalReadLatency 96098615 # Total latency of read requests (Tick)
board.processor.cores1.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores1.generator.totalReads 134210 # Total num of reads (Count)
board.processor.cores1.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores1.generator.avgReadLatency 716.031704 # Avg latency of read requests ((Tick/Count))
board.processor.cores1.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores1.generator.readBW 1073680000 # Read bandwidth ((Byte/Second))
board.processor.cores1.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores1.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores2.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores2.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores2.generator.numRetries 0 # Number of retries (Count)
board.processor.cores2.generator.retryTicks 0 # Time spent waiting due to back-pressure (Tick)
board.processor.cores2.generator.bytesRead 1073680 # Number of bytes read (Byte)
board.processor.cores2.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores2.generator.totalReadLatency 99079764 # Total latency of read requests (Tick)
board.processor.cores2.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores2.generator.totalReads 134210 # Total num of reads (Count)
board.processor.cores2.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores2.generator.avgReadLatency 738.244274 # Avg latency of read requests ((Tick/Count))
board.processor.cores2.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores2.generator.readBW 1073680000 # Read bandwidth ((Byte/Second))
board.processor.cores2.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores2.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores3.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores3.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores3.generator.numRetries 0 # Number of retries (Count)
board.processor.cores3.generator.retryTicks 0 # Time spent waiting due to back-pressure (Tick)
board.processor.cores3.generator.bytesRead 1073680 # Number of bytes read (Byte)
board.processor.cores3.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores3.generator.totalReadLatency 102304967 # Total latency of read requests (Tick)
board.processor.cores3.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores3.generator.totalReads 134210 # Total num of reads (Count)
board.processor.cores3.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores3.generator.avgReadLatency 762.275292 # Avg latency of read requests ((Tick/Count))
board.processor.cores3.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores3.generator.readBW 1073680000 # Read bandwidth ((Byte/Second))
board.processor.cores3.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores3.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores4.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores4.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores4.generator.numRetries 143 # Number of retries (Count)
board.processor.cores4.generator.retryTicks 270806 # Time spent waiting due to back-pressure (Tick)
board.processor.cores4.generator.bytesRead 1073656 # Number of bytes read (Byte)
board.processor.cores4.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores4.generator.totalReadLatency 3185579882 # Total latency of read requests (Tick)
board.processor.cores4.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores4.generator.totalReads 134207 # Total num of reads (Count)
board.processor.cores4.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores4.generator.avgReadLatency 23736.316899 # Avg latency of read requests ((Tick/Count))
board.processor.cores4.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores4.generator.readBW 1073656000 # Read bandwidth ((Byte/Second))
board.processor.cores4.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores4.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores5.generator.numSuppressed 0 # Number of suppressed packets to non-memory space (Count)
board.processor.cores5.generator.numPackets 134210 # Number of packets generated (Count)
board.processor.cores5.generator.numRetries 134 # Number of retries (Count)
board.processor.cores5.generator.retryTicks 282897 # Time spent waiting due to back-pressure (Tick)
board.processor.cores5.generator.bytesRead 1073656 # Number of bytes read (Byte)
board.processor.cores5.generator.bytesWritten 0 # Number of bytes written (Byte)
board.processor.cores5.generator.totalReadLatency 3188449429 # Total latency of read requests (Tick)
board.processor.cores5.generator.totalWriteLatency 0 # Total latency of write requests (Tick)
board.processor.cores5.generator.totalReads 134207 # Total num of reads (Count)
board.processor.cores5.generator.totalWrites 0 # Total num of writes (Count)
board.processor.cores5.generator.avgReadLatency 23757.698399 # Avg latency of read requests ((Tick/Count))
board.processor.cores5.generator.avgWriteLatency nan # Avg latency of write requests ((Tick/Count))
board.processor.cores5.generator.readBW 1073656000 # Read bandwidth ((Byte/Second))
board.processor.cores5.generator.writeBW 0 # Write bandwidth ((Byte/Second))
board.processor.cores5.generator.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------