[board]
type=System
children=cache_hierarchy clk_domain dvfs_handler memory processor workload
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=false
external_memory_ranges=
init_param=0
m5ops_base=0
mem_mode=timing
mem_ranges=0:1073741824
memories=board.memory.module
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
redirect_paths=
shadow_rom_ranges=
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[0]

[board.cache_hierarchy]
type=SubSystem
children=dptw_caches iptw_caches l1dcaches l1icaches membus
eventq_index=0
thermal_domain=Null

[board.cache_hierarchy.dptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.dptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.port_end.req_ports[2]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[4]

[board.cache_hierarchy.dptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.dptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.dptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.dptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.dptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.dptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.iptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.port_end.req_ports[1]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[3]

[board.cache_hierarchy.iptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.iptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.iptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.power_state
prefetcher=board.cache_hierarchy.l1dcaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.generator.port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[2]

[board.cache_hierarchy.l1dcaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1dcaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1dcaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1dcaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1dcaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1dcaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.power_state
prefetcher=board.cache_hierarchy.l1icaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.port_end.req_ports[0]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[1]

[board.cache_hierarchy.l1icaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1icaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1icaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1icaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1icaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1icaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.system_port board.cache_hierarchy.l1icaches.mem_side board.cache_hierarchy.l1dcaches.mem_side board.cache_hierarchy.iptw_caches.mem_side board.cache_hierarchy.dptw_caches.mem_side
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.memory.module.port

[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default

[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board

[board.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=333
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.clk_domain.voltage_domain

[board.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000

[board.memory]
type=SubSystem
children=module
eventq_index=0
thermal_domain=Null

[board.memory.module]
type=SimpleMemory
children=power_state
bandwidth=29.000000
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
latency=20000
latency_var=0
null=false
power_model=
power_state=board.memory.module.power_state
range=0:1073741824
writeable=true
port=board.cache_hierarchy.membus.mem_side_ports[0]

[board.memory.module.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor]
type=SubSystem
children=cores
eventq_index=0
thermal_domain=Null

[board.processor.cores]
type=SubSystem
children=generator port_end
eventq_index=0
thermal_domain=Null

[board.processor.cores.generator]
type=PyTrafficGen
children=power_state
clk_domain=board.clk_domain
cpu_id=-1
elastic_req=false
eventq_index=0
max_outstanding_reqs=0
numThreads=1
power_model=
power_state=board.processor.cores.generator.power_state
progress_check=1000000000
sids=
socket_id=0
ssids=
stream_gen=none
system=board
port=board.cache_hierarchy.l1dcaches.cpu_side

[board.processor.cores.generator.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.port_end]
type=PortTerminator
eventq_index=0
req_ports=board.cache_hierarchy.l1icaches.cpu_side board.cache_hierarchy.iptw_caches.cpu_side board.cache_hierarchy.dptw_caches.cpu_side

[board.workload]
type=StubWorkload
byte_order=little
entry=0
eventq_index=0
remote_gdb_port=#7000
wait_for_remote_gdb=false

[root]
type=Root
children=board
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000