Unit IV Introduction
Welcome to Unit IV! You should now have a good idea of the basics of gem5:
- Use standard library components (boards, processors, cache hierarchies, and memory systems) to run a gem5 simulation,
- Create new standard library components using existing gem5 models to further customize behavior,
- Use both full-system and SE mode simulations,
- Obtain and create gem5 resources to run simulation workloads,
- Make hypercalls from the simulation to the simulator.
One thing we have yet to do is create our own gem5 models. This is the focus of Unit IV!
Unlike the previous units, you may now choose between three tracks for Unit IV depending on which models are more relevant to your work:
- The CPU track, where you will be implementing a new branch predictor,
- The caching track, where you will be implementing a new cache replacement policy,
- The memory track, where you will be implementing [TBD].
All tracks teach similar information through the lens of a different project; you can expect some unique domain-specific details in each track.
You can always go back to the other tracks when you’re done!
By the end of this unit, you will be able to:
- Create gem5 SimObjects with custom parameters, ports, and events.
- Debug gem5 code using C++ and gem5 utilities.
- Code according to gem5’s conventions and best practices.
- Develop gem5 simulations without relying on standard library components.
- Modify an ISA implementation in gem5.
- Implement Ruby cache coherency protocols in gem5.