---------- Begin Simulation Statistics ----------
simSeconds 0.020000 # Number of seconds simulated (Second)
simTicks 20000000000 # Number of ticks simulated (Tick)
finalTick 20000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 185.36 # Real time elapsed on the host (Second)
hostTickRate 107895882 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3735184 # Number of bytes of host memory used (Byte)
simInsts 37817928 # Number of instructions simulated (Count)
simOps 65667824 # Number of ops (including micro ops) simulated (Count)
hostInstRate 204020 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 354264 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.apicbridge.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.bridge.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandHits::processor.cores.core.mmu.dtb.walker 6768 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.dptw_cache.demandHits::total 6768 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.dptw_cache.overallHits::processor.cores.core.mmu.dtb.walker 6768 # number of overall hits (Count)
board.cache_hierarchy.clusters.dptw_cache.overallHits::total 6768 # number of overall hits (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMisses::processor.cores.core.mmu.dtb.walker 297 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMisses::total 297 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMisses::processor.cores.core.mmu.dtb.walker 297 # number of overall misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMisses::total 297 # number of overall misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 1199466 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMissLatency::total 1199466 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 1199466 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMissLatency::total 1199466 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandAccesses::processor.cores.core.mmu.dtb.walker 7065 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandAccesses::total 7065 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallAccesses::processor.cores.core.mmu.dtb.walker 7065 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallAccesses::total 7065 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.042038 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandMissRate::total 0.042038 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.042038 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMissRate::total 0.042038 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 4038.606061 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.demandAvgMissLatency::total 4038.606061 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 4038.606061 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMissLatency::total 4038.606061 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.writebacks::writebacks 2 # number of writebacks (Count)
board.cache_hierarchy.clusters.dptw_cache.writebacks::total 2 # number of writebacks (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 297 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMisses::total 297 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 297 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMisses::total 297 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 1100565 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissLatency::total 1100565 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 1100565 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissLatency::total 1100565 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.042038 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissRate::total 0.042038 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.042038 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissRate::total 0.042038 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3705.606061 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.demandAvgMshrMissLatency::total 3705.606061 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3705.606061 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMshrMissLatency::total 3705.606061 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.replacements 13 # number of replacements (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.hits::processor.cores.core.mmu.dtb.walker 6768 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.hits::total 6768 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.misses::processor.cores.core.mmu.dtb.walker 297 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.misses::total 297 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missLatency::processor.cores.core.mmu.dtb.walker 1199466 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missLatency::total 1199466 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.accesses::processor.cores.core.mmu.dtb.walker 7065 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.accesses::total 7065 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missRate::processor.cores.core.mmu.dtb.walker 0.042038 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missRate::total 0.042038 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 4038.606061 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMissLatency::total 4038.606061 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMisses::processor.cores.core.mmu.dtb.walker 297 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMisses::total 297 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 1100565 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissLatency::total 1100565 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.042038 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissRate::total 0.042038 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3705.606061 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMshrMissLatency::total 3705.606061 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.tagsInUse 19.726824 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.totalRefs 7065 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.sampledRefs 297 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.avgRefs 23.787879 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.warmupTick 368964 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 19.726824 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.154116 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.avgOccs::total 0.154116 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.occupanciesTaskId::1024 25 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ageTaskId_1024::3 14 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ageTaskId_1024::4 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ratioOccsTaskId::1024 0.195312 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.dptw_cache.tags.tagAccesses 28557 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.dataAccesses 28557 # Number of data accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandHits::processor.cores.core.mmu.itb.walker 145 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.iptw_cache.demandHits::total 145 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.iptw_cache.overallHits::processor.cores.core.mmu.itb.walker 145 # number of overall hits (Count)
board.cache_hierarchy.clusters.iptw_cache.overallHits::total 145 # number of overall hits (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMisses::processor.cores.core.mmu.itb.walker 18 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMisses::total 18 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMisses::processor.cores.core.mmu.itb.walker 18 # number of overall misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMisses::total 18 # number of overall misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMissLatency::processor.cores.core.mmu.itb.walker 418581 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMissLatency::total 418581 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMissLatency::processor.cores.core.mmu.itb.walker 418581 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMissLatency::total 418581 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandAccesses::processor.cores.core.mmu.itb.walker 163 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandAccesses::total 163 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallAccesses::processor.cores.core.mmu.itb.walker 163 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallAccesses::total 163 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.110429 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandMissRate::total 0.110429 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.110429 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMissRate::total 0.110429 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 23254.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.demandAvgMissLatency::total 23254.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 23254.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMissLatency::total 23254.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 18 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMisses::total 18 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 18 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMisses::total 18 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 412587 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissLatency::total 412587 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 412587 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissLatency::total 412587 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.110429 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissRate::total 0.110429 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.110429 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissRate::total 0.110429 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 22921.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.demandAvgMshrMissLatency::total 22921.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 22921.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMshrMissLatency::total 22921.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.hits::processor.cores.core.mmu.itb.walker 143 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.hits::total 143 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.misses::processor.cores.core.mmu.itb.walker 18 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.misses::total 18 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missLatency::processor.cores.core.mmu.itb.walker 418581 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missLatency::total 418581 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.accesses::processor.cores.core.mmu.itb.walker 161 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.accesses::total 161 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missRate::processor.cores.core.mmu.itb.walker 0.111801 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missRate::total 0.111801 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMissLatency::processor.cores.core.mmu.itb.walker 23254.500000 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMissLatency::total 23254.500000 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMisses::processor.cores.core.mmu.itb.walker 18 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMisses::total 18 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 412587 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissLatency::total 412587 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.111801 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissRate::total 0.111801 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 22921.500000 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMshrMissLatency::total 22921.500000 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.WriteReq.hits::processor.cores.core.mmu.itb.walker 2 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.hits::total 2 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.accesses::processor.cores.core.mmu.itb.walker 2 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.accesses::total 2 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.tagsInUse 11.416181 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.totalRefs 163 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.sampledRefs 18 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.avgRefs 9.055556 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.warmupTick 84915 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.occupancies::processor.cores.core.mmu.itb.walker 11.416181 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.089189 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.avgOccs::total 0.089189 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.occupanciesTaskId::1024 13 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ageTaskId_1024::3 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ageTaskId_1024::4 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ratioOccsTaskId::1024 0.101562 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.iptw_cache.tags.tagAccesses 670 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.dataAccesses 670 # Number of data accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.demandHits::processor.cores.core.data 11091920 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandHits::total 11091920 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::processor.cores.core.data 11091920 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::total 11091920 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::processor.cores.core.data 360741 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::total 360741 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::processor.cores.core.data 360741 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::total 360741 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::processor.cores.core.data 10760930964 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::total 10760930964 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::processor.cores.core.data 10760930964 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::total 10760930964 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::processor.cores.core.data 11452661 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::total 11452661 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::processor.cores.core.data 11452661 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::total 11452661 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::processor.cores.core.data 0.031498 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::total 0.031498 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::processor.cores.core.data 0.031498 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::total 0.031498 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::processor.cores.core.data 29830.074663 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::total 29830.074663 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::processor.cores.core.data 29830.074663 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::total 29830.074663 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_targets 275 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_targets 2 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_targets 137.500000 # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.writebacks::writebacks 327517 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.writebacks::total 327517 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::processor.cores.core.data 319161 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::total 319161 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::processor.cores.core.data 319161 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::total 319161 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::processor.cores.core.data 41580 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::total 41580 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 301528 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::processor.cores.core.data 41580 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::total 343108 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::processor.cores.core.data 1898993772 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::total 1898993772 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35476633026 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::processor.cores.core.data 1898993772 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::total 37375626798 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheableLatency::processor.cores.core.data 4565373057 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheableLatency::total 4565373057 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::processor.cores.core.data 0.003631 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::total 0.003631 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::processor.cores.core.data 0.003631 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::total 0.029959 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::processor.cores.core.data 45670.845887 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::total 45670.845887 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 117656.181270 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::processor.cores.core.data 45670.845887 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::total 108932.542517 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrUncacheableLatency::processor.cores.core.data 192161.505893 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrUncacheableLatency::total 192161.505893 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.replacements 341959 # number of replacements (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 301528 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::total 301528 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35476633026 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::total 35476633026 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 117656.181270 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::total 117656.181270 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.hits::processor.cores.core.data 14260 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.hits::total 14260 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.misses::processor.cores.core.data 72 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.misses::total 72 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missLatency::processor.cores.core.data 1773225 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missLatency::total 1773225 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.accesses::processor.cores.core.data 14332 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.accesses::total 14332 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missRate::processor.cores.core.data 0.005024 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missRate::total 0.005024 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMissLatency::processor.cores.core.data 24628.125000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMissLatency::total 24628.125000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMisses::processor.cores.core.data 72 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMisses::total 72 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissLatency::processor.cores.core.data 41840451 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissLatency::total 41840451 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissRate::processor.cores.core.data 0.005024 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissRate::total 0.005024 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMshrMissLatency::processor.cores.core.data 581117.375000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMshrMissLatency::total 581117.375000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.hits::processor.cores.core.data 14332 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.hits::total 14332 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.accesses::processor.cores.core.data 14332 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.accesses::total 14332 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::processor.cores.core.data 5145205 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::total 5145205 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::processor.cores.core.data 116991 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::total 116991 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::processor.cores.core.data 3476369817 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::total 3476369817 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::processor.cores.core.data 5262196 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::total 5262196 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::processor.cores.core.data 0.022232 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::total 0.022232 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::processor.cores.core.data 29714.848296 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::total 29714.848296 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::processor.cores.core.data 82850 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::total 82850 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::processor.cores.core.data 34141 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::total 34141 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::processor.cores.core.data 801793737 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::total 801793737 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4565373057 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheableLatency::total 4565373057 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::processor.cores.core.data 0.006488 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::total 0.006488 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::processor.cores.core.data 23484.775988 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::total 23484.775988 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 218941.734941 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrUncacheableLatency::total 218941.734941 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::processor.cores.core.data 5946715 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::total 5946715 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::processor.cores.core.data 243750 # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::total 243750 # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::processor.cores.core.data 7284561147 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::total 7284561147 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::processor.cores.core.data 6190465 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::total 6190465 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::processor.cores.core.data 0.039375 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::total 0.039375 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::processor.cores.core.data 29885.379065 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::total 29885.379065 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::processor.cores.core.data 236311 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::total 236311 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::processor.cores.core.data 7439 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::total 7439 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::processor.cores.core.data 1097200035 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::total 1097200035 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::processor.cores.core.data 0.001202 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::total 0.001202 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::processor.cores.core.data 147492.947305 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::total 147492.947305 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.prefetcher.demandMshrMisses 41580 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIssued 1199940 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUnused 600 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUseful 56191 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulButMiss 140 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.accuracy 0.046828 # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.coverage 0.574721 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInCache 128073 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInMSHR 770339 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfLate 898412 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIdentified 1209236 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfBufferHit 7111 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedDemand 53 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfSpanPage 49796 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulSpanPage 3617 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.tagsInUse 255.913161 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.tags.totalRefs 11463806 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.sampledRefs 342215 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.avgRefs 33.498841 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1dcache.tags.warmupTick 549783 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 152.356955 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::processor.cores.core.data 103.556206 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.595144 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::processor.cores.core.data 0.404516 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::total 0.999661 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1022 243 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1024 13 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1022::0 243 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::0 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::3 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1022 0.949219 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1024 0.050781 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.tagAccesses 92192815 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.dataAccesses 92192815 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.demandHits::processor.cores.core.inst 9065199 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.demandHits::total 9065199 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::processor.cores.core.inst 9065199 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::total 9065199 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::processor.cores.core.inst 11483 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::total 11483 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::processor.cores.core.inst 11483 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::total 11483 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::processor.cores.core.inst 351104877 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::total 351104877 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::processor.cores.core.inst 351104877 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::total 351104877 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandAccesses::processor.cores.core.inst 9076682 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandAccesses::total 9076682 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::processor.cores.core.inst 9076682 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::total 9076682 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissRate::processor.cores.core.inst 0.001265 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMissRate::total 0.001265 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::processor.cores.core.inst 0.001265 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::total 0.001265 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::processor.cores.core.inst 30576.058260 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::total 30576.058260 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::processor.cores.core.inst 30576.058260 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::total 30576.058260 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.writebacks::writebacks 203 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1icache.writebacks::total 203 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrHits::processor.cores.core.inst 1420 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrHits::total 1420 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::processor.cores.core.inst 1420 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::total 1420 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::processor.cores.core.inst 10063 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::total 10063 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::processor.cores.core.inst 10063 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::total 10063 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::processor.cores.core.inst 278871516 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::total 278871516 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::processor.cores.core.inst 278871516 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::total 278871516 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::processor.cores.core.inst 0.001109 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::total 0.001109 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::processor.cores.core.inst 0.001109 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::total 0.001109 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::processor.cores.core.inst 27712.562457 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::total 27712.562457 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::processor.cores.core.inst 27712.562457 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::total 27712.562457 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.replacements 9789 # number of replacements (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::processor.cores.core.inst 9065199 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::total 9065199 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::processor.cores.core.inst 11483 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::total 11483 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::processor.cores.core.inst 351104877 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::total 351104877 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::processor.cores.core.inst 9076682 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::total 9076682 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::processor.cores.core.inst 0.001265 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::total 0.001265 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::processor.cores.core.inst 30576.058260 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::total 30576.058260 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::processor.cores.core.inst 1420 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::total 1420 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::processor.cores.core.inst 10063 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::total 10063 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::processor.cores.core.inst 278871516 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::total 278871516 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::processor.cores.core.inst 0.001109 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::total 0.001109 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::processor.cores.core.inst 27712.562457 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::total 27712.562457 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.prefetcher.demandMshrMisses 10063 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.tags.tagsInUse 242.691000 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.tags.totalRefs 9075262 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.sampledRefs 10063 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.avgRefs 901.844579 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1icache.tags.warmupTick 359640 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1icache.tags.occupancies::processor.cores.core.inst 242.691000 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::processor.cores.core.inst 0.948012 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::total 0.948012 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::3 254 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1icache.tags.tagAccesses 72623519 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.dataAccesses 72623519 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadResp 366894 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WritebackDirty 616199 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::CleanEvict 38840 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::HardPFReq 373935 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::UpgradeReq 960 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::UpgradeResp 960 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExReq 6551 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExResp 6551 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadSharedReq 346047 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 1075824 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 29896 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.iptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 26 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.dptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 343 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount::total 1106089 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 42886456 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 655808 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.iptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 512 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.dptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 2240 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize::total 43545016 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.snoops 677512 # Total snoops (Count)
board.cache_hierarchy.clusters.l2_bus.snoopTraffic 18481536 # Total snoop traffic (Byte)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::samples 1054529 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::mean 0.004915 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::stdev 0.070824 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::0 1049412 99.51% 99.51% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::1 5051 0.48% 99.99% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::2 66 0.01% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::max_value 2 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::total 1054529 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.occupancy 552340477 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer0.occupancy 357048591 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer1.occupancy 10056589 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer2.occupancy 18314 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer3.occupancy 296703 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer3.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totRequests 705319 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleRequests 352452 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiRequests 1073 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totSnoops 4051 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleSnoops 4015 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiSnoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::cache_hierarchy.clusters.l1dcache.prefetcher 40511 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.mmu.dtb.walker 12 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.mmu.itb.walker 1 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.inst 5885 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.data 27523 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::total 73932 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::cache_hierarchy.clusters.l1dcache.prefetcher 40511 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.mmu.dtb.walker 12 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.mmu.itb.walker 1 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.inst 5885 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.data 27523 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::total 73932 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher 261015 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.mmu.dtb.walker 21 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.mmu.itb.walker 7 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.inst 4159 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.data 13167 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::total 278369 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher 261015 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.mmu.dtb.walker 21 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.mmu.itb.walker 7 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.inst 4159 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.data 13167 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::total 278369 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35192199860 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 675324 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.mmu.itb.walker 389277 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.inst 250515900 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.data 1767410820 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::total 37211191181 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35192199860 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 675324 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.mmu.itb.walker 389277 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.inst 250515900 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.data 1767410820 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::total 37211191181 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 301526 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.mmu.dtb.walker 33 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.mmu.itb.walker 8 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.inst 10044 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.data 40690 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::total 352301 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 301526 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.mmu.dtb.walker 33 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.mmu.itb.walker 8 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.inst 10044 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.data 40690 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::total 352301 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.865647 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.636364 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.inst 0.414078 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.data 0.323593 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::total 0.790145 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.865647 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.636364 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.inst 0.414078 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.data 0.323593 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::total 0.790145 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 134828.266038 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 32158.285714 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 55611 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.inst 60234.647752 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.data 134230.334928 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::total 133675.772737 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 134828.266038 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 32158.285714 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 55611 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.inst 60234.647752 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.data 134230.334928 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::total 133675.772737 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.writebacks::writebacks 288456 # number of writebacks (Count)
board.cache_hierarchy.clusters.l2cache.writebacks::total 288456 # number of writebacks (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 254704 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::processor.cores.core.mmu.itb.walker 1 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::processor.cores.core.data 13 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::total 254718 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 254704 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::processor.cores.core.mmu.itb.walker 1 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::processor.cores.core.data 13 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::total 254718 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 6311 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 21 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 6 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.inst 4159 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.data 13154 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::total 23651 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 6311 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 283406 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 21 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 6 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.inst 4159 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.data 13154 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::total 307057 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1835664597 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 668331 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 376290 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.inst 249130953 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.data 1762488414 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::total 3848328585 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1835664597 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61306670797 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 668331 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 376290 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.inst 249130953 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.data 1762488414 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::total 65154999382 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheableLatency::processor.cores.core.data 4537597527 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheableLatency::total 4537597527 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.020930 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.636364 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.inst 0.414078 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.data 0.323274 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::total 0.067133 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.020930 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.636364 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.inst 0.414078 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.data 0.323274 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::total 0.871576 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 290867.469022 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 31825.285714 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 62715 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 59901.647752 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 133988.780143 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::total 162713.144687 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 290867.469022 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 216321.005190 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 31825.285714 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 62715 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 59901.647752 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 133988.780143 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::total 212191.871157 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrUncacheableLatency::processor.cores.core.data 190992.403696 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrUncacheableLatency::total 190992.403696 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.replacements 302982 # number of replacements (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMisses::writebacks 922 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMisses::total 922 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMissRate::writebacks inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMissRate::total inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 283406 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::total 283406 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61306670797 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::total 61306670797 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 216321.005190 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::total 216321.005190 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::processor.cores.core.data 1389 # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::total 1389 # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::processor.cores.core.data 5161 # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::total 5161 # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::processor.cores.core.data 1085074839 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::total 1085074839 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::processor.cores.core.data 6550 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::total 6550 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::processor.cores.core.data 0.787939 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::total 0.787939 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 210245.076342 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::total 210245.076342 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 5161 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::total 5161 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 1083356226 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::total 1083356226 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.787939 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::total 0.787939 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 209912.076342 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::total 209912.076342 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4537597527 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheableLatency::total 4537597527 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 217609.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadReq.avgMshrUncacheableLatency::total 217609.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::cache_hierarchy.clusters.l1dcache.prefetcher 40511 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.mmu.dtb.walker 12 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.mmu.itb.walker 1 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.inst 5885 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.data 26134 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::total 72543 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher 261015 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.mmu.dtb.walker 21 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.mmu.itb.walker 7 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.inst 4159 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.data 8006 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::total 273208 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35192199860 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.mmu.dtb.walker 675324 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.mmu.itb.walker 389277 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 250515900 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 682335981 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::total 36126116342 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher 301526 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.mmu.dtb.walker 33 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.mmu.itb.walker 8 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 10044 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.data 34140 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::total 345751 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.865647 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.mmu.dtb.walker 0.636364 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.414078 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.data 0.234505 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::total 0.790187 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 134828.266038 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 32158.285714 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.itb.walker 55611 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 60234.647752 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 85228.076568 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::total 132229.350319 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 254704 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::processor.cores.core.mmu.itb.walker 1 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::processor.cores.core.data 13 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::total 254718 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 6311 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.dtb.walker 21 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.itb.walker 6 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 4159 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 7993 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::total 18490 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1835664597 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 668331 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 376290 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 249130953 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 679132188 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::total 2764972359 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.020930 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.636364 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.414078 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.234124 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::total 0.053478 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 290867.469022 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 31825.285714 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 62715 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 59901.647752 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 84965.868635 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::total 149538.797134 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.hits::processor.cores.core.data 946 # number of UpgradeReq hits (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.hits::total 946 # number of UpgradeReq hits (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.misses::processor.cores.core.data 12 # number of UpgradeReq misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.misses::total 12 # number of UpgradeReq misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missLatency::processor.cores.core.data 104895 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missLatency::total 104895 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.accesses::processor.cores.core.data 958 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.accesses::total 958 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missRate::processor.cores.core.data 0.012526 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missRate::total 0.012526 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMissLatency::processor.cores.core.data 8741.250000 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMissLatency::total 8741.250000 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMisses::processor.cores.core.data 12 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMisses::total 12 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissLatency::processor.cores.core.data 135864 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissLatency::total 135864 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissRate::processor.cores.core.data 0.012526 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissRate::total 0.012526 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores.core.data 11322 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMshrMissLatency::total 11322 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::writebacks 327722 # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::total 327722 # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::writebacks 327722 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::total 327722 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.prefetcher.demandMshrMisses 23651 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIssued 1066222 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUnused 629 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUseful 28055 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.accuracy 0.026313 # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.coverage 0.542587 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInCache 44197 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInMSHR 738619 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfLate 782816 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIdentified 1126258 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfBufferHit 38277 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedDemand 13143 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfSpanPage 46146 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulSpanPage 1146 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.tags.tagsInUse 4087.171459 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.tags.totalRefs 732746 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.sampledRefs 307078 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.avgRefs 2.386189 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l2cache.tags.warmupTick 84249 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l2cache.tags.occupancies::writebacks 3.265117 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 117.278950 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher 3262.740866 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 0.663467 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.mmu.itb.walker 0.367312 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.inst 280.260314 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.data 422.595433 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::writebacks 0.000797 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.028633 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher 0.796568 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.000162 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.000090 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.inst 0.068423 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.data 0.103173 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::total 0.997845 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1022 4025 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1024 71 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::0 275 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::1 2412 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::2 1338 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::0 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::1 38 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::2 21 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::3 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1022 0.982666 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1024 0.017334 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.tagAccesses 11586966 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.dataAccesses 11586966 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iocache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iocache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iocache.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iocache.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadResp 322738 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WritebackDirty 444916 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::CleanEvict 26005 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::UpgradeReq 14 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::UpgradeResp 12 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExReq 5161 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExResp 5161 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadSharedReq 301895 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.pktCount_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port 964317 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l3_bus.pktSize_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port 38136056 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l3_bus.snoops 168251 # Total snoops (Count)
board.cache_hierarchy.l3_bus.snoopTraffic 10013440 # Total snoop traffic (Byte)
board.cache_hierarchy.l3_bus.snoopFanout::samples 499077 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::mean 0.000593 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::stdev 0.024346 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::0 498781 99.94% 99.94% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::1 296 0.06% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::total 499077 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.occupancy 466765448 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.respLayer0.occupancy 321599079 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.snoop_filter.totRequests 609742 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleRequests 302714 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.totSnoops 296 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleSnoops 296 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_cache.demandHits::cache_hierarchy.clusters.l1dcache.prefetcher 283 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::cache_hierarchy.clusters.l2cache.prefetcher 4910 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.mmu.dtb.walker 16 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.mmu.itb.walker 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.inst 1260 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.data 1256 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::total 7727 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.overallHits::cache_hierarchy.clusters.l1dcache.prefetcher 283 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::cache_hierarchy.clusters.l2cache.prefetcher 4910 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.mmu.dtb.walker 16 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.mmu.itb.walker 2 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.inst 1260 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.data 1256 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::total 7727 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.mmu.dtb.walker 5 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.mmu.itb.walker 4 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.inst 2899 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.data 11898 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::total 299329 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.mmu.dtb.walker 5 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.mmu.itb.walker 4 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.inst 2899 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.data 11898 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::total 299329 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1806586167 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61144795755 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 471528 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.mmu.itb.walker 337662 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.inst 223670772 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.data 1700704260 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::total 64876566144 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1806586167 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61144795755 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 471528 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.mmu.itb.walker 337662 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.inst 223670772 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.data 1700704260 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::total 64876566144 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 8777 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l2cache.prefetcher 280939 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.mmu.dtb.walker 21 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.mmu.itb.walker 6 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.inst 4159 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.data 13154 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::total 307056 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 8777 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l2cache.prefetcher 280939 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.mmu.dtb.walker 21 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.mmu.itb.walker 6 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.inst 4159 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.data 13154 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::total 307056 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.238095 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.inst 0.697043 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.data 0.904516 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::total 0.974835 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.238095 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.inst 0.697043 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.data 0.904516 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::total 0.974835 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212689.682953 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221515.839839 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 94305.600000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 84415.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.inst 77154.457399 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.data 142940.347958 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::total 216739.995603 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212689.682953 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221515.839839 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 94305.600000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 84415.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.inst 77154.457399 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.data 142940.347958 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::total 216739.995603 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.writebacks::writebacks 156460 # number of writebacks (Count)
board.cache_hierarchy.l3_cache.writebacks::total 156460 # number of writebacks (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 5 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 4 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.inst 2899 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.data 11898 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::total 299329 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 5 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 4 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.inst 2899 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.data 11898 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::total 299329 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l3_cache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1803757665 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61052881095 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 469863 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 336330 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.inst 222705405 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.data 1696742226 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::total 64776892584 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1803757665 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61052881095 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 469863 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 336330 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.inst 222705405 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.data 1696742226 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::total 64776892584 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrUncacheableLatency::processor.cores.core.data 4440385503 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrUncacheableLatency::total 4440385503 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.238095 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.inst 0.697043 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.data 0.904516 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::total 0.974835 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.238095 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.inst 0.697043 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.data 0.904516 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::total 0.974835 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212356.682953 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221182.850697 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 93972.600000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 84082.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.inst 76821.457399 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.data 142607.347958 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::total 216407.005616 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212356.682953 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221182.850697 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 93972.600000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 84082.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.inst 76821.457399 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.data 142607.347958 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::total 216407.005616 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrUncacheableLatency::processor.cores.core.data 186900.644120 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrUncacheableLatency::total 186900.644120 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.replacements 168249 # number of replacements (Count)
board.cache_hierarchy.l3_cache.ReadExReq.hits::processor.cores.core.data 349 # number of ReadExReq hits (Count)
board.cache_hierarchy.l3_cache.ReadExReq.hits::total 349 # number of ReadExReq hits (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::processor.cores.core.data 4812 # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::total 4812 # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::processor.cores.core.data 1060139466 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::total 1060139466 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::processor.cores.core.data 5161 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::total 5161 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::processor.cores.core.data 0.932377 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::total 0.932377 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::processor.cores.core.data 220311.609726 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::total 220311.609726 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::processor.cores.core.data 4812 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::total 4812 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::processor.cores.core.data 1058537070 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::total 1058537070 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.932377 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::total 0.932377 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 219978.609726 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::total 219978.609726 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4440385503 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheableLatency::total 4440385503 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 212947.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadReq.avgMshrUncacheableLatency::total 212947.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::cache_hierarchy.clusters.l1dcache.prefetcher 283 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::cache_hierarchy.clusters.l2cache.prefetcher 4910 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.mmu.dtb.walker 16 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.mmu.itb.walker 2 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.inst 1260 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.data 907 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::total 7378 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.mmu.dtb.walker 5 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.mmu.itb.walker 4 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.inst 2899 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.data 7086 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::total 294517 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1806586167 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l2cache.prefetcher 61144795755 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.mmu.dtb.walker 471528 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.mmu.itb.walker 337662 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.inst 223670772 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.data 640564794 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::total 63816426678 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher 8777 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l2cache.prefetcher 280939 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.mmu.dtb.walker 21 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.mmu.itb.walker 6 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.inst 4159 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.data 7993 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::total 301895 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.mmu.dtb.walker 0.238095 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.inst 0.697043 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.data 0.886526 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::total 0.975561 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212689.682953 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221515.839839 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 94305.600000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.itb.walker 84415.500000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 77154.457399 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 90398.644369 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::total 216681.640374 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 276029 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.dtb.walker 5 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.itb.walker 4 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 2899 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.data 7086 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::total 294517 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1803757665 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61052881095 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 469863 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 336330 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 222705405 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 638205156 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::total 63718355514 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.967757 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.982523 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.238095 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.697043 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.886526 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::total 0.975561 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 212356.682953 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 221182.850697 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 93972.600000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 84082.500000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 76821.457399 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 90065.644369 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::total 216348.650550 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.UpgradeReq.hits::processor.cores.core.data 12 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.hits::total 12 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.accesses::processor.cores.core.data 12 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.accesses::total 12 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.hits::writebacks 288456 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.hits::total 288456 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.accesses::writebacks 288456 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.accesses::total 288456 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_cache.tags.tagsInUse 101756.989669 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l3_cache.tags.totalRefs 609731 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.sampledRefs 299321 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.avgRefs 2.037047 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l3_cache.tags.warmupTick 83583 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l3_cache.tags.occupancies::writebacks 0.101009 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 4371.419469 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher 90461.640816 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 3.636820 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.mmu.itb.walker 2.740170 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.inst 1286.221656 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.data 5631.229729 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::writebacks 0.000001 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.033351 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher 0.690168 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.000028 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.000021 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.inst 0.009813 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.data 0.042963 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::total 0.776344 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1022 129023 # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1024 2049 # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::0 275 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::1 2412 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::2 24137 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::3 102199 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::0 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::1 38 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::2 383 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::3 1623 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1022 0.984367 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1024 0.015633 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.tagAccesses 10055161 # Number of tag accesses (Count)
board.cache_hierarchy.l3_cache.tags.dataAccesses 10055161 # Number of data accesses (Count)
board.cache_hierarchy.l3_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadResp 315360 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 156460 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 11514 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::UpgradeReq 2 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 4812 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 4812 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 294517 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.bridge.cpu_side_port 47512 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port 766625 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.processor.cores.core.interrupts.pio 4 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::total 814141 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 814141 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.bridge.cpu_side_port 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port 29169920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.processor.cores.core.interrupts.pio 8 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::total 29193784 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 29193784 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 2 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 323185 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 323185 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 323185 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 8878446 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 209082840 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer2.occupancy 666 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 265482651 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 467836 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 168411 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.iobus.transDist::ReadReq 20850 # Transaction distribution (Count)
board.iobus.transDist::ReadResp 20850 # Transaction distribution (Count)
board.iobus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.iobus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 35846 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 4 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.com_1.pio 11594 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.pci_host.pio 68 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::total 47512 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount::total 47512 # Packet count per connected requestor and responder (Count)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 17923 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 2 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.com_1.pio 5797 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.pci_host.pio 134 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::total 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize::total 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.reqLayer10.occupancy 2896767 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer10.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer15.occupancy 11322 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer15.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer7.occupancy 5969358 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer7.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer8.occupancy 999 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer8.utilization 0.0 # Layer utilization (Ratio)
board.iobus.respLayer0.occupancy 20381337 # Layer occupancy (ticks) (Tick)
board.iobus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.memory.mem_ctrl.avgPriority_writebacks::samples 312920.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l1dcache.prefetcher::samples 16988.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l2cache.prefetcher::samples 552058.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.dtb.walker::samples 10.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.itb.walker::samples 8.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 5798.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 23796.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000022500 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.009638443476 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 19552 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 19553 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 617852 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 296471 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 299329 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 156460 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 598658 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 312920 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 7.80 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 26.16 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 96 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 435 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 598658 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 312920 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 15254 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 15591 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 14080 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 14213 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 11670 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 13973 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 11684 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 11855 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 13760 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 12621 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 12099 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 41622 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 154678 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 132562 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 34314 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 34369 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 27532 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 18389 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 578 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 689 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 525 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 1180 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 1464 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 816 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 436 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 287 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 237 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 207 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 241 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 235 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 777 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 720 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 5 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 16 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 82 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 87 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 145 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 146 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 190 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 193 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 237 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 237 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 298 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 299 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 354 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 361 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 453 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 452 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 538 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 529 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 537 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 542 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 613 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 625 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 958 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 955 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 1434 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 1453 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 2286 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 2302 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 3440 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 3509 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 5280 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 5571 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 8125 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 8028 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 10656 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 11057 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 19953 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 20097 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 18581 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 26047 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 38103 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 62058 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 37720 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 6038 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 4457 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 5399 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 2007 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 449 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples 19553 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean 30.616325 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean 16.261761 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev 1461.045045 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::0-8191 19552 99.99% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total 19553 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples 19552 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean 16.001023 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean 16.000841 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev 0.091022 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16 19547 99.97% 99.97% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17 1 0.01% 99.98% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18 2 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19 1 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total 19552 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 19157056 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 10013440 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 957852800.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 500672000.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 19999978995 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 43879.91 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l1dcache.prefetcher 543616 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l2cache.prefetcher 17665312 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.dtb.walker 320 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.itb.walker 256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 185536 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 761472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks 10011552 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l1dcache.prefetcher 27180800.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l2cache.prefetcher 883265600.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.dtb.walker 16000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.itb.walker 12800.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 9276800.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 38073600.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 500577600.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 16988 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l2cache.prefetcher 552058 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.dtb.walker 10 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.itb.walker 8 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 5798 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 23796 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks 312920 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l1dcache.prefetcher 3010538074 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l2cache.prefetcher 100626263526 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.dtb.walker 596556 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.itb.walker 398022 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 245787624 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 2574735154 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks 512703663448 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l1dcache.prefetcher 177215.57 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l2cache.prefetcher 182274.80 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.dtb.walker 59655.60 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.itb.walker 49752.75 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 42391.79 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 108200.33 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks 1638449.65 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l1dcache.prefetcher 543616 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l2cache.prefetcher 17665280 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.dtb.walker 320 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.itb.walker 256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 185536 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 761472 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 19156480 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 185536 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 185536 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks 10013440 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total 10013440 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l1dcache.prefetcher 8494 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l2cache.prefetcher 276020 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.dtb.walker 5 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.itb.walker 4 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 2899 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 11898 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 299320 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks 156460 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total 156460 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l1dcache.prefetcher 27180800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l2cache.prefetcher 883264000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.dtb.walker 16000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.itb.walker 12800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 9276800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 38073600 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 957824000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 9276800 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 9276800 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks 500672000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total 500672000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks 500672000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l1dcache.prefetcher 27180800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l2cache.prefetcher 883264000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.dtb.walker 16000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.itb.walker 12800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 9276800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 38073600 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 1458496000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 598641 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 312861 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 74944 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 74996 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 74622 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 74690 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 74596 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 74999 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 74870 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 74924 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 39086 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 39146 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 39060 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 39051 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 39026 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 39204 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 39216 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 39072 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 92988896456 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 4489807500 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 106458318956 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 155333.32 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 7500.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 177833.32 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 553126 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 277046 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 92.40 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate 88.55 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 81330 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 358.638436 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 281.236952 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 185.600961 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-63 734 0.90% 0.90% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::64-127 13564 16.68% 17.58% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-191 6467 7.95% 25.53% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::192-255 4888 6.01% 31.54% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-319 4000 4.92% 36.46% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::320-383 3013 3.70% 40.16% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-447 2512 3.09% 43.25% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::448-511 2915 3.58% 46.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-575 43237 53.16% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 81330 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 19156512 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 10011552 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 957.825600 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 500.577600 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 4266.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 34.19 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 22.45 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 11.73 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 91.08 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 247400492.220002 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 87148742.553598 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 1028265052.449601 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 482451103.848004 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 142953704.460019 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 416091465.594024 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 385155025.516779 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 2789465586.642066 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 139.473279 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 9544550242 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 669110000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 9786339758 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.bad_addr.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.com_1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.default_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.empty_isa.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_2.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_3.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_4.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_floppy.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.cmos.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.dma1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadFullPages 0 # Number of full page size DMA reads (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadBytes 0 # Number of bytes transfered via DMA reads (not PRD). (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadTxs 0 # Number of DMA read transactions (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteFullPages 0 # Number of full page size DMA writes. (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteBytes 0 # Number of bytes transfered via DMA writes. (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteTxs 0 # Number of DMA write transactions. (Count)
board.pc.south_bridge.ide.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.io_apic.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.keyboard.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic2.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pit.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.speaker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 60060061 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.588137 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.629668 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 81297266 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded 200586 # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued 77939836 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 1719553 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 15830028 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 9606267 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved 51198 # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples 59645719 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 1.306713 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 2.452762 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 43616471 73.13% 73.13% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 2197108 3.68% 76.81% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 1471242 2.47% 79.28% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 876473 1.47% 80.75% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 1201291 2.01% 82.76% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 2131111 3.57% 86.33% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 4034589 6.76% 93.10% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 2436900 4.09% 97.18% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 1680534 2.82% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 59645719 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 2084312 87.84% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 87.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 168736 7.11% 94.95% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 119933 5.05% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 4779657 6.13% 6.13% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 59990893 76.97% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 383 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 799 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 83.10% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 6758407 8.67% 91.78% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 6409697 8.22% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 77939836 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 1.297698 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 2372981 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.030446 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 208556930 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 84716326 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 72536068 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 11060995 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 12628118 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 75533160 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numRecvResp 11505082 # Number of received responses (Count)
board.processor.cores.core.numRecvRespBytes 80490431 # Number of received response bytes (Byte)
board.processor.cores.core.recvRespAvgBW 1.34 # Average bandwidth of received responses ((Byte/Cycle))
board.processor.cores.core.recvRespAvgSize 7.00 # Average packet size per received response ((Byte/Count))
board.processor.cores.core.recvRespAvgRate 0.19 # Average rate of received responses per cycle ((Count/Cycle))
board.processor.cores.core.recvRespAvgRetryRate 0.00 # Average retry rate per received response ((Count/Count))
board.processor.cores.core.numSendRetryResp 0 # Number of retry responses sent (Count)
board.processor.cores.core.numSquashedInsts 1631444 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 3166 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 414342 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 6973533 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 6500819 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 604999 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 265610 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 822632 7.26% 7.26% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 1657993 14.64% 21.90% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 1680876 14.84% 36.74% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 27768 0.25% 36.98% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 4892232 43.19% 80.18% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 2245509 19.82% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 2 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 11327012 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 816873 25.65% 25.65% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 213280 6.70% 32.35% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 263127 8.26% 40.61% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 798 0.03% 40.63% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 1404525 44.10% 84.73% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 486247 15.27% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 1 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 3184851 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 359027 35.63% 35.63% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 358912 35.62% 71.25% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 20005 1.99% 73.23% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 393 0.04% 73.27% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 267436 26.54% 99.81% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 1881 0.19% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 1 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 1007655 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 5759 0.07% 0.07% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 1444713 17.74% 17.81% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 1417749 17.41% 35.23% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 26970 0.33% 35.56% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 3487701 42.84% 78.39% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 1759262 21.61% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 1 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 8142155 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 5759 1.11% 1.11% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 349105 67.39% 68.50% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 18094 3.49% 72.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 366 0.07% 72.07% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 143317 27.67% 99.73% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 1376 0.27% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 1 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 518018 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch 5759 4.07% 4.07% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return 2 0.00% 4.07% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect 1 0.00% 4.07% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect 0 0.00% 4.07% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond 135821 95.93% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total 141583 # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return 349103 92.74% 92.74% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect 18093 4.81% 97.55% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect 366 0.10% 97.64% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond 7496 1.99% 99.63% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond 1376 0.37% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond 1 0.00% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total 376435 # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 3776996 33.35% 33.35% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 5865291 51.78% 85.13% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 1657947 14.64% 99.76% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 26778 0.24% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 11327012 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 77646 15.25% 15.25% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 72713 14.28% 29.52% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 358910 70.48% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 3 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 509272 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 5596486 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 1878235 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 1007655 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 34217 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups 11327012 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 222145 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 7908468 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.698195 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 35254 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 27769 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 26778 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 991 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 822632 7.26% 7.26% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 1657993 14.64% 21.90% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 1680876 14.84% 36.74% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 27768 0.25% 36.98% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 4892232 43.19% 80.18% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 2245509 19.82% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 2 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 11327012 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 23167 0.68% 0.68% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 1657953 48.50% 49.18% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 21323 0.62% 49.80% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 27768 0.81% 50.61% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 1685406 49.30% 99.91% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 2925 0.09% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 2 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 3418544 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 20005 9.01% 9.01% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 9.01% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 200259 90.15% 99.15% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 1881 0.85% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 222145 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 20005 9.01% 9.01% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 9.01% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 200259 90.15% 99.15% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 1881 0.85% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 222145 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 27769 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 26778 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 991 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 394 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 28164 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 2 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 1921924 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 1921918 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 477205 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 1444713 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 1095608 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 349105 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 15829993 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.commitNonSpecStalls 149388 # The number of times commit has been forced to stall to communicate backwards (Count)
board.processor.cores.core.commit.branchMispredicts 929183 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 56846665 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 1.155175 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.405832 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 42038794 73.95% 73.95% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 2955254 5.20% 79.15% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 1904994 3.35% 82.50% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 2444181 4.30% 86.80% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 1048216 1.84% 88.64% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 829008 1.46% 90.10% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 702324 1.24% 91.34% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 372961 0.66% 91.99% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 4550933 8.01% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 56846665 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 76244 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 1444719 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 24092 0.04% 0.04% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 53400159 81.32% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 343 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 769 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 81.36% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 6035386 9.19% 90.55% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 6207075 9.45% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 65667824 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 4550933 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 37817928 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 65667824 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 37817928 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 65667824 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.588137 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.629668 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 12242461 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 61196223 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 6035386 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 6207075 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 24092 0.04% 0.04% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 53400159 81.32% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 343 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 769 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 81.36% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 6035386 9.19% 90.55% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 6207075 9.45% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 65667824 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 8142155 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 6664712 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 1471684 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 3487701 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 4654447 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 1444719 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 1444713 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 2439530 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 42492253 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 12051969 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 1715026 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 946941 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 5298328 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 83129 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 91982018 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 469326 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 76301725 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 9449451 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 6651842 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 6337962 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 1.270424 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 26816775 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 24262019 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 76965541 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 48026058 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 12989804 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 30224539 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numMiscRegWrites 58095 # Number of times the Misc registers were written (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 7550016 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 57925166 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 2050826 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.tlbCycles 512 # Number of cycles fetch has spent waiting for tlb (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 5 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 9076682 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 3269 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.tlbSquashes 10 # Number of outstanding ITLB misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 59645719 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 1.695644 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 2.940950 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 42187413 70.73% 70.73% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 779603 1.31% 72.04% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 1162823 1.95% 73.99% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 2687382 4.51% 78.49% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 1093198 1.83% 80.32% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 1955734 3.28% 83.60% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 874631 1.47% 85.07% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 668242 1.12% 86.19% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 8236693 13.81% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 59645719 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 43598969 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.725923 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 11327012 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.188595 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 694623 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 946941 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 1906338 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 321164 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 81497852 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 4711 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 6973533 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 6500819 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 122650 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 1428 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 319534 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 19238 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 446805 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 636338 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 1083143 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 76245509 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 72536068 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 42694949 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 65189927 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 1.207726 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.654932 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 1353942 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 938147 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 54 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 19238 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 293744 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 523 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 2 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 6035386 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 6.120810 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 44.210739 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 5904056 97.82% 97.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 46835 0.78% 98.60% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 878 0.01% 98.61% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39 1428 0.02% 98.64% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 3039 0.05% 98.69% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59 524 0.01% 98.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69 7963 0.13% 98.83% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79 18027 0.30% 99.13% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89 8681 0.14% 99.27% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99 210 0.00% 99.28% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 118 0.00% 99.28% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119 154 0.00% 99.28% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 426 0.01% 99.29% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 457 0.01% 99.29% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 185 0.00% 99.30% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 1216 0.02% 99.32% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 2986 0.05% 99.37% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 1908 0.03% 99.40% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 108 0.00% 99.40% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 181 0.00% 99.40% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 1604 0.03% 99.43% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 2162 0.04% 99.47% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 609 0.01% 99.48% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 122 0.00% 99.48% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 1781 0.03% 99.51% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259 494 0.01% 99.52% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269 1020 0.02% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::270-279 88 0.00% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::280-289 144 0.00% 99.54% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::290-299 2398 0.04% 99.58% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 25584 0.42% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1525 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 6035386 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.addedLoadsAndStores 13474352 # Number of loads and stores written to the Load Store Queue (Count)
board.processor.cores.core.mmu.dtb.rdAccesses 6637432 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 6335948 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 6427 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 243 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 9076745 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 54 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 946941 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 3316484 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 3658810 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 16596493 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 12865008 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 22261983 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 87881487 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 59573 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 168380 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 13990 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents 21823380 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 119978550 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 230031604 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 81819171 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.committedMaps 103105743 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 16872807 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 108235 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 104902 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 5205046 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rename.intReturned 43306150 # count of registers freed and written back to integer free list (Count)
board.processor.cores.core.rob.reads 133787701 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 166190903 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 37817928 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 65667824 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------