---------- Begin Simulation Statistics ----------
simSeconds 0.000030 # Number of seconds simulated (Second)
simTicks 30008000 # Number of ticks simulated (Tick)
finalTick 30008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 1083634263 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 1507304 # Number of bytes of host memory used (Byte)
simInsts 5166 # Number of instructions simulated (Count)
simOps 6027 # Number of ops (including micro ops) simulated (Count)
hostInstRate 185787 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 216682 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 1754 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 1754 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 1756 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 1756 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 137 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 137 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 139 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 139 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 7758000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 7758000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 7758000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 7758000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 1891 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 1891 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 1895 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 1895 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.072448 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.072448 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.073351 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.073351 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 56627.737226 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 56627.737226 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 55812.949640 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 55812.949640 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 2 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 2 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 2 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 2 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 135 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 135 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 37 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 137 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 174 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 7579000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 7579000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 1944911 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 7691000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 9635911 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.071391 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.071391 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.072296 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.091821 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 56140.740741 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 56140.740741 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 52565.162162 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 56138.686131 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 55378.798851 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 37 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 37 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 1944911 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 1944911 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 52565.162162 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 52565.162162 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::processor.cores.core.data 15 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::total 15 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::processor.cores.core.data 1 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::total 1 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missLatency::processor.cores.core.data 50000 # number of LoadLockedReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missLatency::total 50000 # number of LoadLockedReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::processor.cores.core.data 16 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::total 16 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::processor.cores.core.data 0.062500 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::total 0.062500 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMissLatency::processor.cores.core.data 50000 # average LoadLockedReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMissLatency::total 50000 # average LoadLockedReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMisses::processor.cores.core.data 1 # number of LoadLockedReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMisses::total 1 # number of LoadLockedReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissLatency::processor.cores.core.data 49000 # number of LoadLockedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissLatency::total 49000 # number of LoadLockedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissRate::processor.cores.core.data 0.062500 # mshr miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissRate::total 0.062500 # mshr miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMshrMissLatency::processor.cores.core.data 49000 # average LoadLockedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMshrMissLatency::total 49000 # average LoadLockedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 737 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 737 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 80 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 80 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 4300000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 4300000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 817 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 817 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.097919 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.097919 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 53750 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 53750 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data 2 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total 2 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 78 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 78 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 4178000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 4178000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.095471 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.095471 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 53564.102564 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 53564.102564 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.SoftPFReq.hits::processor.cores.core.data 2 # number of SoftPFReq hits (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.hits::total 2 # number of SoftPFReq hits (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.misses::processor.cores.core.data 2 # number of SoftPFReq misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.misses::total 2 # number of SoftPFReq misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.accesses::processor.cores.core.data 4 # number of SoftPFReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.accesses::total 4 # number of SoftPFReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.missRate::processor.cores.core.data 0.500000 # miss rate for SoftPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFReq.missRate::total 0.500000 # miss rate for SoftPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMisses::processor.cores.core.data 2 # number of SoftPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMisses::total 2 # number of SoftPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMissLatency::processor.cores.core.data 112000 # number of SoftPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMissLatency::total 112000 # number of SoftPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMissRate::processor.cores.core.data 0.500000 # mshr miss rate for SoftPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFReq.mshrMissRate::total 0.500000 # mshr miss rate for SoftPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFReq.avgMshrMissLatency::processor.cores.core.data 56000 # average SoftPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.SoftPFReq.avgMshrMissLatency::total 56000 # average SoftPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::processor.cores.core.data 16 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::total 16 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::processor.cores.core.data 16 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::total 16 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 1017 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 1017 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 57 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 57 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 3458000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 3458000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 1074 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 1074 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.053073 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.053073 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 60666.666667 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 60666.666667 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 57 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 57 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 3401000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 3401000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.053073 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.053073 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 59666.666667 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 59666.666667 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 135 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 125 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 33 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.264000 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.196429 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 60 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 28 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 88 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 125 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 3 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 2 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 107.458313 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 1962 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 175 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 11.211429 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 143000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 27.266229 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 80.192084 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.026627 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.078313 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.104940 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 37 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 138 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 37 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 40 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 98 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.036133 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.134766 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 15591 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 15591 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 4903 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 4903 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 4903 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 4903 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 277 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 277 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 277 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 277 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 15508000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 15508000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 15508000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 15508000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 5180 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 5180 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 5180 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 5180 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.053475 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.053475 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.053475 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.053475 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 55985.559567 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 55985.559567 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 55985.559567 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 55985.559567 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 277 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 277 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 277 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 277 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 15231000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 15231000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 15231000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 15231000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.053475 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.053475 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.053475 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.053475 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 54985.559567 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 54985.559567 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 54985.559567 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 54985.559567 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 4903 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 4903 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 277 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 277 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 15508000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 15508000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 5180 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 5180 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.053475 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.053475 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 55985.559567 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 55985.559567 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 277 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 277 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 15231000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 15231000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.053475 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.053475 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 54985.559567 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 54985.559567 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 277 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 126.961815 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 5180 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 277 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 18.700361 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 76000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 126.961815 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.123986 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.123986 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 277 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 108 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1 169 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 0.270508 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 41717 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 41717 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 395 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 57 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 57 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 395 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 554 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total 554 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 350 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total 350 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 904 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 17728 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total 17728 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 11200 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total 11200 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 28928 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 452 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0.033186 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0.179320 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 437 96.68% 96.68% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 15 3.32% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 452 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 477922 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 683198 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 430900 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 452 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 1000 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 37.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 277.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 138.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000693652 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 910 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 452 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 452 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 1.04 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 452 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 439 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 5 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 28928 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 964009597.44068241 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 29956000 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 66274.34 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 2368 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 17728 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 8832 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 78912290.055985063314 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 590775793.121834158897 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 294321514.262863218784 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 37 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 277 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 138 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 779524 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 6505802 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 3393576 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 21068.22 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 23486.65 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 24591.13 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 2368 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 17728 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 8832 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 28928 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 17728 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 17728 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 37 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 277 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 138 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 452 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 78912290 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 590775793 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 294321514 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 964009597 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 590775793 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 590775793 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 78912290 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 590775793 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 294321514 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 964009597 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 452 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 78 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 36 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 35 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 11 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 13 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 19 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 36 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 19 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 23 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 12 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 34 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 3 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 6 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 3 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 2 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 7 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 5 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 13 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 63 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 2772518 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 1506064 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 10678902 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 6133.89 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 23625.89 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 359 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 79.42 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 81 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 303.407407 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 191.635227 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 307.729174 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 22 27.16% 58.02% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 13 16.05% 74.07% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 5 6.17% 80.25% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 1 1.23% 81.48% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 5 6.17% 87.65% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 1 1.23% 88.89% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 1 1.23% 90.12% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 8 9.88% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 81 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 28928 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 964.009597 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 5.02 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 5.02 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 79.42 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 104478.192000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 159668.107200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 940815.523200 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 2027566.648800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 14148394.377600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 27461.011200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 17408383.860000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 580.124762 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 1000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 1050000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 28957000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 40543.776000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 63316.663200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 298976.361600 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 2027566.648800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 13543846.293600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 444814.003200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 16419063.746400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 547.156217 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 1251160 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 1050000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 27706840 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 30008 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 5.795288 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.172554 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.commitStats0.numInsts 5178 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 6041 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 5.795288 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.172554 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 5434 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 837 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 1093 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 248 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 3 0.05% 0.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 3954 65.45% 65.50% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 4 0.07% 65.57% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 4 0.07% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 65.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 100 1.66% 67.29% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 67.29% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 15 0.25% 67.54% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 67.54% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 10 0.17% 67.70% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 12 0.20% 67.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 67.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 9 0.15% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 68.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 837 13.86% 81.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 1093 18.09% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 6041 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1082 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 955 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 127 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 800 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 282 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 95 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 91 # Class of control type instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns 186 # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles 0.001000 # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 30007.999000 # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction 1.000000 # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction 0.000000 # Percentage of idle cycles (Ratio)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 1930 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntAluAccesses 5434 # Number of integer alu accesses (Count)
board.processor.cores.core.executeStats0.numIntRegReads 6491 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 3555 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 1930 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 519 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numMiscRegWrites 33 # Number of times the Misc registers were written (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 248 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numVecRegReads 197 # Number of times the vector registers were read (Count)
board.processor.cores.core.executeStats0.numVecRegWrites 157 # Number of times the vector registers were written (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetchStats0.numInsts 5178 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 6041 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.172554 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1082 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.036057 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.mmu.alignFaults 0 # Number of MMU faults due to alignment restrictions (Count)
board.processor.cores.core.mmu.prefetchFaults 0 # Number of MMU faults due to prefetch (Count)
board.processor.cores.core.mmu.domainFaults 0 # Number of MMU faults due to domain restrictions (Count)
board.processor.cores.core.mmu.permsFaults 0 # Number of MMU faults due to permissions restrictions (Count)
board.processor.cores.core.mmu.dtb.readHits 0 # Read hits (Count)
board.processor.cores.core.mmu.dtb.readMisses 0 # Read misses (Count)
board.processor.cores.core.mmu.dtb.writeHits 0 # Write hits (Count)
board.processor.cores.core.mmu.dtb.writeMisses 0 # Write misses (Count)
board.processor.cores.core.mmu.dtb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.dtb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.dtb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.dtb.readAccesses 0 # Read accesses (Count)
board.processor.cores.core.mmu.dtb.writeAccesses 0 # Write accesses (Count)
board.processor.cores.core.mmu.dtb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.dtb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.dtb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.dtb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.instHits 0 # Inst hits (Count)
board.processor.cores.core.mmu.itb.instMisses 0 # Inst misses (Count)
board.processor.cores.core.mmu.itb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.itb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.itb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.itb.instAccesses 0 # Inst accesses (Count)
board.processor.cores.core.mmu.itb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.itb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.itb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.itb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.l2_shared.instHits 0 # Inst hits (Count)
board.processor.cores.core.mmu.l2_shared.instMisses 0 # Inst misses (Count)
board.processor.cores.core.mmu.l2_shared.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.l2_shared.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.l2_shared.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.l2_shared.instAccesses 0 # Inst accesses (Count)
board.processor.cores.core.mmu.l2_shared.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.l2_shared.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.l2_shared.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.readHits 0 # Read hits (Count)
board.processor.cores.core.mmu.stage2_dtb.readMisses 0 # Read misses (Count)
board.processor.cores.core.mmu.stage2_dtb.writeHits 0 # Write hits (Count)
board.processor.cores.core.mmu.stage2_dtb.writeMisses 0 # Write misses (Count)
board.processor.cores.core.mmu.stage2_dtb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.stage2_dtb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.stage2_dtb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.stage2_dtb.readAccesses 0 # Read accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.writeAccesses 0 # Write accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.stage2_dtb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.stage2_dtb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.stage2_itb.instHits 0 # Inst hits (Count)
board.processor.cores.core.mmu.stage2_itb.instMisses 0 # Inst misses (Count)
board.processor.cores.core.mmu.stage2_itb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.stage2_itb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.stage2_itb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.stage2_itb.instAccesses 0 # Inst accesses (Count)
board.processor.cores.core.mmu.stage2_itb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.stage2_itb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.stage2_itb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_itb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 30008000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 10 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------