---------- Begin Simulation Statistics ----------
simSeconds 0.000000 # Number of seconds simulated (Second)
simTicks 72927 # Number of ticks simulated (Tick)
finalTick 72927 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 0.03 # Real time elapsed on the host (Second)
hostTickRate 2590473 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3384276 # Number of bytes of host memory used (Byte)
simInsts 1 # Number of instructions simulated (Count)
simOps 5 # Number of ops (including micro ops) simulated (Count)
hostInstRate 35 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 177 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandMisses::processor.cores.core.inst 2 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::total 2 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::processor.cores.core.inst 2 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::total 2 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::processor.cores.core.inst 69930 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::total 69930 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::processor.cores.core.inst 69930 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::total 69930 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.cores.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.cores.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissRate::processor.cores.core.inst 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMissRate::total 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::processor.cores.core.inst 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::total 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::processor.cores.core.inst 34965 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::total 34965 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::processor.cores.core.inst 34965 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::total 34965 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::processor.cores.core.inst 2 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::total 2 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::processor.cores.core.inst 2 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::total 2 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::processor.cores.core.inst 69597 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::total 69597 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::processor.cores.core.inst 69597 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::total 69597 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::total 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::total 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 34798.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::total 34798.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 34798.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::total 34798.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::processor.cores.core.inst 2 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::total 2 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::processor.cores.core.inst 69930 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::total 69930 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.cores.core.inst 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 2 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::processor.cores.core.inst 1 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::total 1 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::processor.cores.core.inst 34965 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::total 34965 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::processor.cores.core.inst 2 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::total 2 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::processor.cores.core.inst 69597 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::total 69597 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::processor.cores.core.inst 1 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::total 1 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.inst 34798.500000 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::total 34798.500000 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 2 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 0.041109 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.cores.core.inst 0.041109 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.cores.core.inst 0.000080 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.000080 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 1 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::0 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 0.001953 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 17 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 17 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.inst 2 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::total 2 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.inst 2 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::total 2 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.inst 68931 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::total 68931 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.inst 68931 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::total 68931 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.inst 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::total 2 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.inst 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::total 2 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.inst 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::total 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.inst 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::total 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.inst 34465.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::total 34465.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.inst 34465.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::total 34465.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.inst 2 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::total 2 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.inst 2 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::total 2 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.inst 68598 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::total 68598 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.inst 68598 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::total 68598 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::total 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::total 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 34299 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::total 34299 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 34299 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::total 34299 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.inst 2 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::total 2 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.inst 68931 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::total 68931 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.inst 2 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::total 2 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.inst 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::total 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.inst 34465.500000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::total 34465.500000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.inst 2 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::total 2 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 68598 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::total 68598 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.inst 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::total 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 34299 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::total 34299 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 2 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 0.050241 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.inst 0.050241 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.inst 0.000012 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.000012 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 1 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::0 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.000244 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 33 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 33 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.transDist::ReadResp 1 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadSharedReq 2 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 3 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount::total 3 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 64 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize::total 64 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 2 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 2 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 2 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.reqLayer0.occupancy 666 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer0.occupancy 999 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 2 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.transDist::ReadResp 1 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 1 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::total 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 64 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::total 64 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 64 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 1 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 1 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 1 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer1.occupancy 333 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 788 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 1 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 0.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 23926.425600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 23926.425600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 328.087342 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 72927 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 23926.425600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 23926.425600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 328.087342 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 72927 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.inst::samples 1.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000041483 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000041483 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 2 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 1 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 1 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 0.94 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 1 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 64 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 877589918.68580902 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 0.00 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.inst 64 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.inst 877589918.685809016228 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.inst 1 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.inst 41483 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.inst 41483.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.inst 64 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 64 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores.core.inst 64 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 64 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.inst 1 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 1 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.inst 877589919 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 877589919 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores.core.inst 877589919 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 877589919 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.inst 877589919 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 877589919 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 1 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 23991 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 3332 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 41483 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 23991.00 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 41483.00 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 0.00 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 64 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 877.589919 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 4.57 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 4.57 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 0.00 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 1559.376000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 2742.902400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 32295.076800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 1631.347200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 38228.702400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 524.205060 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 4329 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 68598 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 23926.425600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 23926.425600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 328.087342 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 72927 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 219 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 219.000000 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.004566 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 5 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.instsIssued 5 # Number of instructions issued (Count)
board.processor.cores.core.numIssuedDist::samples 20 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 0.250000 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 0.786398 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 18 90.00% 90.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 0 0.00% 90.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 1 5.00% 95.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 1 5.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 3 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 20 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 4 80.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 0 0.00% 80.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 1 20.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 5 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 0.022831 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 0 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 30 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 5 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 5 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 5 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numSquashedInsts 0 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 199 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 1 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 1 50.00% 50.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 0 0.00% 50.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 1 50.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 2 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 1 100.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 1 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 1 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 1 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 0 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 0 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 2 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 2 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 1 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 1 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 1 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 0 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 1 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 1 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.NotTakenMispredicted 1 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.cores.core.branchPred.TakenMispredicted 0 # Number branches predicted taken but are actually not taken (Count)
board.processor.cores.core.branchPred.BTBLookups 2 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 1 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 0 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.000000 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 1 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 1 50.00% 50.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 0 0.00% 50.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 1 50.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 2 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 1 50.00% 50.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 0 0.00% 50.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 1 50.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 0 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 0 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 2 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 1 100.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 1 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 1 100.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 1 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 1 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.numCommittedDist::samples 20 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 0.250000 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 0.786398 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 18 90.00% 90.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 0 0.00% 90.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 1 5.00% 95.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 1 5.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 3 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 20 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 1 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 4 80.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 0 0.00% 80.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 1 20.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 5 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 0 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 1 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 5 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 1 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 5 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 219.000000 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.004566 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 1 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 5 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 1 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 4 80.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 0 0.00% 80.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 1 20.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 5 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 1 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 1 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 18 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.runCycles 1 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.branchResolved 1 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 1 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 5 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 8 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 5 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 1 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 1 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0.022831 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 5 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 3 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 1 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 3 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.cycles 2 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 2 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.cacheLines 2 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.nisnDist::samples 20 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 0.800000 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 2.462348 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 18 90.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 0 0.00% 90.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 2 10.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 20 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 8 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.036530 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 2 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.009132 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 17 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 0 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 0 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 5 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 0 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 1 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 0 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 0 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 0 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 5 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 5 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 2 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 3 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 0.022831 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.666667 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 0 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 0 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 0 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 0 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 1 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 1 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 2 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 1 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 72927 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 72927 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.idleCycles 19 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 0 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.renamedInsts 5 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.renamedOperands 3 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 9 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 5 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.committedMaps 2 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 0 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads 25 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 10 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 1 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 5 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 0 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000323 # Number of seconds simulated (Second)
simTicks 323450559 # Number of ticks simulated (Tick)
finalTick 323523486 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 5.05 # Real time elapsed on the host (Second)
hostTickRate 64040282 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3423092 # Number of bytes of host memory used (Byte)
simInsts 1000001 # Number of instructions simulated (Count)
simOps 1992440 # Number of ops (including micro ops) simulated (Count)
hostInstRate 197987 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 394476 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.cores.core.data 440454 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 440454 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.cores.core.data 440454 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 440454 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::processor.cores.core.data 2648 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::total 2648 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::processor.cores.core.data 2648 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::total 2648 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::processor.cores.core.data 109056168 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::total 109056168 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::processor.cores.core.data 109056168 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::total 109056168 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.cores.core.data 443102 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 443102 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.cores.core.data 443102 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 443102 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissRate::processor.cores.core.data 0.005976 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMissRate::total 0.005976 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::processor.cores.core.data 0.005976 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::total 0.005976 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::processor.cores.core.data 41184.353474 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::total 41184.353474 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::processor.cores.core.data 41184.353474 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::total 41184.353474 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 2 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 2 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs 1 # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.writebacks::writebacks 486 # number of writebacks (Count)
board.cache_hierarchy.l1d-cache-0.writebacks::total 486 # number of writebacks (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::processor.cores.core.data 1438 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::total 1438 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::processor.cores.core.data 1438 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::total 1438 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::processor.cores.core.data 1210 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::total 1210 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 773 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::processor.cores.core.data 1210 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::total 1983 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::processor.cores.core.data 50689926 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::total 50689926 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 30268738 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::processor.cores.core.data 50689926 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::total 80958664 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::processor.cores.core.data 0.002731 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::total 0.002731 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::processor.cores.core.data 0.002731 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::total 0.004475 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 41892.500826 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::total 41892.500826 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 39157.487710 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 41892.500826 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::total 40826.356026 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.replacements 1471 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 773 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::total 773 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 30268738 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::total 30268738 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 39157.487710 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::total 39157.487710 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.hits::processor.cores.core.data 3 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.hits::total 3 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.misses::processor.cores.core.data 1 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missLatency::processor.cores.core.data 4662 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missLatency::total 4662 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.accesses::processor.cores.core.data 4 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.accesses::total 4 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missRate::processor.cores.core.data 0.250000 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missRate::total 0.250000 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMissLatency::processor.cores.core.data 4662 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMissLatency::total 4662 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMisses::processor.cores.core.data 1 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissLatency::processor.cores.core.data 17316 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissLatency::total 17316 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissRate::processor.cores.core.data 0.250000 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissRate::total 0.250000 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMshrMissLatency::processor.cores.core.data 17316 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMshrMissLatency::total 17316 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.hits::processor.cores.core.data 4 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.hits::total 4 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.accesses::processor.cores.core.data 4 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.accesses::total 4 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.cores.core.data 227440 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 227440 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::processor.cores.core.data 2403 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::total 2403 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::processor.cores.core.data 97548354 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::total 97548354 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.cores.core.data 229843 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 229843 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::processor.cores.core.data 0.010455 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::total 0.010455 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::processor.cores.core.data 40594.404494 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::total 40594.404494 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::processor.cores.core.data 1425 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::total 1425 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::processor.cores.core.data 978 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::total 978 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::processor.cores.core.data 39502458 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::total 39502458 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::processor.cores.core.data 0.004255 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::total 0.004255 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.data 40391.061350 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::total 40391.061350 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.cores.core.data 213014 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 213014 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::processor.cores.core.data 245 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::total 245 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::processor.cores.core.data 11507814 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::total 11507814 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.cores.core.data 213259 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 213259 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::processor.cores.core.data 0.001149 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::total 0.001149 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::processor.cores.core.data 46970.669388 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::total 46970.669388 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrHits::processor.cores.core.data 13 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrHits::total 13 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::processor.cores.core.data 232 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::total 232 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::processor.cores.core.data 11187468 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::total 11187468 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::processor.cores.core.data 0.001088 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::total 0.001088 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::processor.cores.core.data 48221.844828 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::total 48221.844828 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 1210 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 2305 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUnused 281 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 380 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy 0.164859 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage 0.238994 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 726 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 806 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 1532 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 2741 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 342 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 20 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 467 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 101 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 482.257032 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 442445 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 1983 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs 223.119012 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 133533 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 180.124888 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.cores.core.data 302.132144 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.351806 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.cores.core.data 0.590102 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 0.941908 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1022 200 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 312 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1022::2 200 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 312 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1022 0.390625 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 0.609375 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3546863 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3546863 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.cores.core.inst 22282 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 22282 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.cores.core.inst 22282 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 22282 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::processor.cores.core.inst 1652 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::total 1652 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::processor.cores.core.inst 1652 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::total 1652 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::processor.cores.core.inst 76493430 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::total 76493430 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::processor.cores.core.inst 76493430 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::total 76493430 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.cores.core.inst 23934 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 23934 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.cores.core.inst 23934 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 23934 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissRate::processor.cores.core.inst 0.069023 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMissRate::total 0.069023 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::processor.cores.core.inst 0.069023 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::total 0.069023 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::processor.cores.core.inst 46303.529056 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::total 46303.529056 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::processor.cores.core.inst 46303.529056 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::total 46303.529056 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.writebacks::writebacks 681 # number of writebacks (Count)
board.cache_hierarchy.l1i-cache-0.writebacks::total 681 # number of writebacks (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::processor.cores.core.inst 460 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::total 460 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::processor.cores.core.inst 460 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::total 460 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::processor.cores.core.inst 1192 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::total 1192 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::processor.cores.core.inst 1192 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::total 1192 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::processor.cores.core.inst 58266342 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::total 58266342 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::processor.cores.core.inst 58266342 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::total 58266342 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::processor.cores.core.inst 0.049804 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::total 0.049804 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::processor.cores.core.inst 0.049804 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::total 0.049804 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 48881.159396 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::total 48881.159396 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 48881.159396 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::total 48881.159396 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.replacements 681 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.cores.core.inst 22282 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 22282 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::processor.cores.core.inst 1652 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::total 1652 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::processor.cores.core.inst 76493430 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::total 76493430 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.cores.core.inst 23934 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 23934 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::processor.cores.core.inst 0.069023 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::total 0.069023 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::processor.cores.core.inst 46303.529056 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::total 46303.529056 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::processor.cores.core.inst 460 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::total 460 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::processor.cores.core.inst 1192 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::total 1192 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::processor.cores.core.inst 58266342 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::total 58266342 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::processor.cores.core.inst 0.049804 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::total 0.049804 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.inst 48881.159396 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::total 48881.159396 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 1192 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 493.259968 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 23476 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 1194 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs 19.661642 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.cores.core.inst 493.259968 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.cores.core.inst 0.963398 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.963398 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 512 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 192665 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 192665 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.demandHits::cache_hierarchy.l1d-cache-0.prefetcher 222 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::processor.cores.core.inst 41 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::processor.cores.core.data 256 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::total 519 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::cache_hierarchy.l1d-cache-0.prefetcher 222 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::processor.cores.core.inst 41 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::processor.cores.core.data 256 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::total 519 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::cache_hierarchy.l1d-cache-0.prefetcher 551 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.inst 1150 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.data 954 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::total 2655 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::cache_hierarchy.l1d-cache-0.prefetcher 551 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.inst 1150 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.data 954 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::total 2655 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.demandMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 28802890 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.inst 57276666 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.data 48883734 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::total 134963290 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 28802890 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.inst 57276666 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.data 48883734 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::total 134963290 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandAccesses::cache_hierarchy.l1d-cache-0.prefetcher 773 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.inst 1191 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.data 1210 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::total 3174 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::cache_hierarchy.l1d-cache-0.prefetcher 773 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.inst 1191 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.data 1210 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::total 3174 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712807 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.inst 0.965575 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.data 0.788430 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::total 0.836484 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712807 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.inst 0.965575 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.data 0.788430 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::total 0.836484 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 52273.847550 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.inst 49805.796522 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.data 51240.811321 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::total 50833.630885 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 52273.847550 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.inst 49805.796522 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.data 51240.811321 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::total 50833.630885 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.demandMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 160 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::processor.cores.core.data 4 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::total 164 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 160 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::processor.cores.core.data 4 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::total 164 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 391 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.inst 1150 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.data 950 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::total 2491 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 391 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l2-cache-0.prefetcher 455 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.inst 1150 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.data 950 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::total 2946 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 22117450 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.inst 56893383 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.data 48473145 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::total 127483978 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 22117450 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 23600981 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.inst 56893383 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.data 48473145 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::total 151084959 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.505821 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.inst 0.965575 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.data 0.785124 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::total 0.784814 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.505821 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.inst 0.965575 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.data 0.785124 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::total 0.928166 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 56566.368286 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 49472.506957 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 51024.363158 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::total 51177.831393 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 56566.368286 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 51870.287912 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 49472.506957 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 51024.363158 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::total 51284.779022 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.replacements 11 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l2-cache-0.prefetcher 455 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::total 455 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 23600981 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::total 23600981 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 51870.287912 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::total 51870.287912 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.hits::processor.cores.core.data 29 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.hits::total 29 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::processor.cores.core.data 203 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::total 203 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::processor.cores.core.data 10923732 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::total 10923732 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::processor.cores.core.data 232 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::total 232 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::processor.cores.core.data 0.875000 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::total 0.875000 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::processor.cores.core.data 53811.487685 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::total 53811.487685 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrHits::processor.cores.core.data 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrHits::total 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::processor.cores.core.data 202 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::total 202 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::processor.cores.core.data 10842480 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::total 10842480 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::processor.cores.core.data 0.870690 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::total 0.870690 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::processor.cores.core.data 53675.643564 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::total 53675.643564 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::cache_hierarchy.l1d-cache-0.prefetcher 222 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::processor.cores.core.inst 41 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::processor.cores.core.data 227 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::total 490 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::cache_hierarchy.l1d-cache-0.prefetcher 551 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.inst 1150 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.data 751 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::total 2452 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::cache_hierarchy.l1d-cache-0.prefetcher 28802890 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.inst 57276666 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.data 37960002 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::total 124039558 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::cache_hierarchy.l1d-cache-0.prefetcher 773 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.inst 1191 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.data 978 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::total 2942 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712807 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.inst 0.965575 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.data 0.767894 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::total 0.833447 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 52273.847550 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.inst 49805.796522 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.data 50545.941411 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::total 50587.095432 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::cache_hierarchy.l1d-cache-0.prefetcher 160 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::processor.cores.core.data 3 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::total 163 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 391 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.inst 1150 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.data 748 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::total 2289 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 22117450 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 56893383 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.data 37630665 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::total 116641498 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.505821 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.965575 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.764826 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::total 0.778042 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 56566.368286 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 49472.506957 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 50308.375668 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::total 50957.404107 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.UpgradeReq.hits::processor.cores.core.data 1 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.hits::total 1 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.accesses::processor.cores.core.data 1 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.accesses::total 1 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.hits::writebacks 681 # number of WritebackClean hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.hits::total 681 # number of WritebackClean hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.accesses::writebacks 681 # number of WritebackClean accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.accesses::total 681 # number of WritebackClean accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.hits::writebacks 486 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.hits::total 486 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.accesses::writebacks 486 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.accesses::total 486 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 2491 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 1259 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUnused 1 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 226 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy 0.179508 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage 0.083180 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 350 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 454 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 804 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 1474 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 116 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 55 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 182 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 35 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2553.409555 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 5620 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 2951 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs 1.904439 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 2.209671 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 329.571231 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 380.706970 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.inst 1016.151001 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.data 824.770682 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000539 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.080462 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.092946 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.inst 0.248084 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.data 0.201360 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.623391 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 844 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2096 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 844 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 2096 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.206055 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.511719 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 88182 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 88182 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.transDist::ReadResp 2944 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::WritebackDirty 486 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::WritebackClean 681 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::CleanEvict 996 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::HardPFReq 563 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::UpgradeReq 1 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::UpgradeResp 1 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExReq 232 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExResp 232 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadSharedReq 2943 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 3065 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 5439 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount::total 8504 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 119872 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 158016 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize::total 277888 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.snoops 575 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 64 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 3750 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean 0.002667 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev 0.051578 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 3740 99.73% 99.73% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 10 0.27% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 3750 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.reqLayer0.occupancy 2638605 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer0.occupancy 1191807 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer1.occupancy 1981350 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 5328 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 2153 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 8 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 8 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.transDist::ReadResp 2745 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 3 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 202 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 202 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 2745 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 2972 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 2925 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::total 5897 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 5897 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 95040 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 93568 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::total 188608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 188608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 2947 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 2947 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 2947 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 540908 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 537872 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 2408679 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 2950 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 193.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 230.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.inst::samples 576.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.data::samples 486.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000747456 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 3038 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 1485 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 1485 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 2.57 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 1485 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 997 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 291 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 104 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 53 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 28 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 8 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 4 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 95040 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 293831614.61780006 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 91529379 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 61635.95 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 12352 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 14720 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.inst 36864 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.data 31104 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 38188216.579956501722 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 45509273.644507750869 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.inst 113971050.518419414759 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.data 96163073.874916374683 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 193 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 230 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.inst 576 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.data 486 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 5412603 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 6594462 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.inst 12585246 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.data 12107618 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 28044.58 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 28671.57 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.inst 21849.39 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.data 24912.79 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 12352 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 14720 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.inst 36864 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.data 31104 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 95040 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores.core.inst 36864 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 36864 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 193 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 230 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.inst 576 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.data 486 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 1485 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 38188217 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 45509274 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.inst 113971051 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.data 96163074 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 293831615 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores.core.inst 113971051 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 113971051 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 38188217 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 45509274 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.inst 113971051 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.data 96163074 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 293831615 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 1485 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 38 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 56 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 40 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 86 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 40 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 63 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 110 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 77 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 28 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 67 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 25 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 40 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 16 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 22 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 93 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 50 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 19 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 37 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 78 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 74 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 89 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 66 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 42 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 64 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 29 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 28 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 24 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 29 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 19 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 16 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 19 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 10724309 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 4948020 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 36699929 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 7221.76 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 24713.76 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 1276 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 85.93 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 209 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 454.736842 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 308.132328 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 345.440539 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 39 18.66% 18.66% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 30 14.35% 33.01% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::256-383 35 16.75% 49.76% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::384-511 23 11.00% 60.77% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::512-639 14 6.70% 67.46% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::640-767 16 7.66% 75.12% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::768-895 10 4.78% 79.90% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::896-1023 6 2.87% 82.78% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 36 17.22% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 209 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 95040 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 293.831615 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 1.53 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 1.53 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 85.93 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 185565.744000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 327594.909600 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 2199807.724800 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 27710077.533600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 45955894.286400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 73848368.832000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 150227309.030400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 464.452155 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 225528306 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 14350000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 83572253 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 140343.840000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 247760.856000 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 1873402.339200 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 27710077.533600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 39741848.899200 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 78138268.185600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 147851701.653600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 457.107578 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 238684650 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 14350000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 70415909 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 198.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 225.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.inst::samples 575.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.data::samples 464.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000724092 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 2994 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 1462 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 1462 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.87 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 1462 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 965 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 278 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 117 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 62 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 25 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 9 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 4 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 93568 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 289280687.25334924 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 91675899 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 62705.81 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 12672 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 14400 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.inst 36800 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.data 29696 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 39177548.615706674755 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 44519941.608757585287 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.inst 113773184.111269369721 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.data 91810012.917615637183 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 198 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 225 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.inst 575 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.data 464 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 6033955 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 6152957 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.inst 13050997 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.data 10548711 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 30474.52 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 27346.48 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.inst 22697.39 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.data 22734.29 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 12672 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 14400 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.inst 36800 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.data 29696 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 93568 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores.core.inst 36800 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 36800 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 198 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 225 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.inst 575 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.data 464 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 1462 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 39177549 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 44519942 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.inst 113773184 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.data 91810013 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 289280687 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores.core.inst 113773184 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 113773184 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 39177549 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 44519942 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.inst 113773184 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.data 91810013 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 289280687 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 1462 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 35 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 59 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 41 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 90 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 43 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 68 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 105 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 75 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 24 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 68 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 22 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 38 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 13 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 21 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 88 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 46 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 10 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 37 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 74 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 69 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 87 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 63 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 46 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 61 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 31 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 32 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 30 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 31 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 22 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 16 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 16 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 10213316 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 4871384 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 35786620 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 6985.85 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 24477.85 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 1255 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 85.84 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 208 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 450.153846 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 306.899854 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 342.223894 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::0-127 37 17.79% 17.79% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 39 18.75% 36.54% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 24 11.54% 48.08% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::384-511 25 12.02% 60.10% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::512-639 21 10.10% 70.19% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::640-767 15 7.21% 77.40% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::768-895 8 3.85% 81.25% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::896-1023 2 0.96% 82.21% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 37 17.79% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 208 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 93568 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 289.280687 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 1.51 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 1.51 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 85.84 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 190243.872000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 338606.503200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 2169635.798400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 27710077.533600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 43647977.822400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 75441651.264000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 149498192.793600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 462.197973 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 230410429 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 14350000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 78690130 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 132546.960000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 233996.364000 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 1840487.510400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 27710077.533600 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 37430387.853600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 79733997.638400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 147081493.860000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 454.726355 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 243573353 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 14350000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 65527206 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 971323 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 0.971323 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 1.029524 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 2097667 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued 2061589 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 1710 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 105164 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 188018 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples 886298 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 2.326068 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 1.605536 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 124553 14.05% 14.05% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 185029 20.88% 34.93% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 158699 17.91% 52.84% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 231644 26.14% 78.97% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 107186 12.09% 91.07% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 56993 6.43% 97.50% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 10336 1.17% 98.66% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 6359 0.72% 99.38% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 5499 0.62% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 886298 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 7372 83.48% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 83.48% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 15 0.17% 83.65% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 83.65% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 12 0.14% 83.78% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 4 0.05% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 83.83% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 967 10.95% 94.78% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 421 4.77% 99.55% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 9 0.10% 99.65% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 31 0.35% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 2625 0.13% 0.13% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 1197432 58.08% 58.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 1738 0.08% 58.29% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 1535 0.07% 58.37% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 716 0.03% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 58.40% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 512 0.02% 58.43% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 58.43% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 1674 0.08% 58.51% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 4 0.00% 58.51% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 1296 0.06% 58.57% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 1141 0.06% 58.63% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 58.63% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 58.63% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 58.63% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 521 0.03% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 58.65% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 632986 30.70% 89.36% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 216053 10.48% 99.84% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 2000 0.10% 99.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 1356 0.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 2061589 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 2.122455 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 8831 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.004284 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 5000558 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 2184541 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 2044978 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 19456 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 18467 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 8917 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 2058086 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 9709 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numSquashedInsts 5330 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 747 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 85025 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 639624 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 220219 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 405457 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 104500 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 514 0.37% 0.37% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 1498 1.07% 1.44% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 1765 1.26% 2.71% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 174 0.12% 2.83% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 133561 95.66% 98.49% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 1577 1.13% 99.62% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.62% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 536 0.38% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 139625 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 474 2.42% 2.42% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 710 3.63% 6.05% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 1060 5.42% 11.47% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 89 0.45% 11.93% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 16082 82.21% 94.14% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 815 4.17% 98.30% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 98.30% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 332 1.70% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 19562 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 89 2.91% 2.91% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 1 0.03% 2.94% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 270 8.82% 11.76% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 89 2.91% 14.66% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 2246 73.35% 88.01% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 231 7.54% 95.56% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 95.56% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 136 4.44% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 3062 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 40 0.03% 0.03% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 788 0.66% 0.69% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 706 0.59% 1.28% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 85 0.07% 1.35% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 117472 97.85% 99.20% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 762 0.63% 99.83% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 99.83% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 204 0.17% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 120057 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 40 1.59% 1.59% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 1.59% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 148 5.90% 7.49% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 85 3.39% 10.88% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 2000 79.68% 90.56% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 115 4.58% 95.14% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 95.14% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 122 4.86% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 2510 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 21627 15.49% 15.49% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 116369 83.34% 98.83% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 1498 1.07% 99.91% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 131 0.09% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 139625 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 2199 78.12% 78.12% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 599 21.28% 99.40% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 1 0.04% 99.43% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 16 0.57% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 2815 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 134075 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 115112 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 3062 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 686 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.NotTakenMispredicted 2443 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.cores.core.branchPred.TakenMispredicted 619 # Number branches predicted taken but are actually not taken (Count)
board.processor.cores.core.branchPred.BTBLookups 139625 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 2128 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 125390 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.898048 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 1141 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 710 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 131 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 579 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 514 0.37% 0.37% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 1498 1.07% 1.44% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 1765 1.26% 2.71% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 174 0.12% 2.83% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 133561 95.66% 98.49% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 1577 1.13% 99.62% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.62% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 536 0.38% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 139625 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 154 1.08% 1.08% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 1498 10.52% 11.61% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 436 3.06% 14.67% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 174 1.22% 15.89% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 11118 78.10% 93.99% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 319 2.24% 96.23% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 96.23% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 536 3.77% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 14235 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 270 12.69% 12.69% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 12.69% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 1627 76.46% 89.14% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 231 10.86% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 2128 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 270 12.69% 12.69% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 12.69% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 1627 76.46% 89.14% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 231 10.86% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 2128 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 710 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 131 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 579 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 225 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 935 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 6 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 2649 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 2647 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 1859 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 788 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 788 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 103307 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards (Count)
board.processor.cores.core.commit.branchMispredicts 2759 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 870997 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 2.287534 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.673532 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 225475 25.89% 25.89% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 310362 35.63% 61.52% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 107984 12.40% 73.92% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 6318 0.73% 74.64% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 3149 0.36% 75.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 100383 11.53% 86.53% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 2490 0.29% 86.82% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 988 0.11% 86.93% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 113848 13.07% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 870997 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 8 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 790 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 1210 0.06% 0.06% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 1145554 57.50% 57.56% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 1689 0.08% 57.64% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 1411 0.07% 57.71% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 389 0.02% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 57.73% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 396 0.02% 57.75% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 57.75% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 862 0.04% 57.79% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 4 0.00% 57.79% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 910 0.05% 57.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 950 0.05% 57.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 57.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 57.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 57.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 190 0.01% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 57.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 624613 31.35% 89.25% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 212177 10.65% 99.90% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 995 0.05% 99.95% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 1085 0.05% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 1992435 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 113848 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 1000000 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 1992435 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 1000000 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 1992435 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 0.971323 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 1.029524 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 838870 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 6131 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 1986917 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 625608 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 213262 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 1210 0.06% 0.06% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 1145554 57.50% 57.56% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 1689 0.08% 57.64% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 1411 0.07% 57.71% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 389 0.02% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 57.73% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 396 0.02% 57.75% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 57.75% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 862 0.04% 57.79% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 4 0.00% 57.79% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 910 0.05% 57.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 950 0.05% 57.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 57.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 57.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 57.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 190 0.01% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 57.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 624613 31.35% 89.25% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 212177 10.65% 99.90% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 995 0.05% 99.95% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 1085 0.05% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 1992435 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 120056 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 118939 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 1077 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 117472 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 2544 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 790 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 788 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 141945 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 469109 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 39515 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 232696 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 3033 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 114557 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 538 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 2136955 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 2719 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 2056256 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 124564 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 634031 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 216968 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 2.116964 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 624797 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 888499 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegReads 13050 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 7157 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 2495054 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 1589664 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 850999 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 1102648 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 117998 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 843462 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 7116 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 1658 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 23934 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 848 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 886298 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 2.465431 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 3.317389 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 524252 59.15% 59.15% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 3827 0.43% 59.58% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 54438 6.14% 65.72% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 4262 0.48% 66.21% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 51836 5.85% 72.05% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 4441 0.50% 72.56% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 55584 6.27% 78.83% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 4699 0.53% 79.36% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 182959 20.64% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 886298 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 1096579 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 1.128954 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 139625 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.143747 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 37384 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 3033 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 49100 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 973 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 2097682 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 149 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 639624 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 220219 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 5 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 265 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 538 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 165 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 755 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 2519 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 3274 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 2055455 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 2053895 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 1609936 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 1836585 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 2.114533 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.876592 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 404010 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 13988 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 165 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 6947 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 625607 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.351919 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 7.582105 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 623879 99.72% 99.72% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 303 0.05% 99.77% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 14 0.00% 99.77% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39 9 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 10 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59 2 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69 5 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79 8 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89 7 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99 15 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 9 0.00% 99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119 17 0.00% 99.79% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 27 0.00% 99.79% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 616 0.10% 99.89% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 304 0.05% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 46 0.01% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 15 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 63 0.01% 99.96% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 220 0.04% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 9 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 6 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1256 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 625607 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses 634070 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 216971 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 310 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 70 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 24176 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 363 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 323450559 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 3033 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 171314 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 75070 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 1893 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 241786 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 393198 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 2122574 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 1619 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 10107 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 347535 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents 7792 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 4075377 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 7712668 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 2588968 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups 21393 # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps 3842955 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 232241 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 74 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 59 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 906589 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads 2851292 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 4206968 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 1000000 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 1992435 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 31 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------