---------- Begin Simulation Statistics ----------
simSeconds 0.000260 # Number of seconds simulated (Second)
simTicks 259588818 # Number of ticks simulated (Tick)
finalTick 1066360572 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 4.63 # Real time elapsed on the host (Second)
hostTickRate 56096771 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3387368 # Number of bytes of host memory used (Byte)
simInsts 1000002 # Number of instructions simulated (Count)
simOps 2000781 # Number of ops (including micro ops) simulated (Count)
hostInstRate 216094 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 432355 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.cores.core.data 444731 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444731 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.cores.core.data 444731 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444731 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::processor.cores.core.data 33 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::total 33 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::processor.cores.core.data 33 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::total 33 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::processor.cores.core.data 1154178 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::total 1154178 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::processor.cores.core.data 1154178 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::total 1154178 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.cores.core.data 444764 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444764 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.cores.core.data 444764 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444764 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissRate::processor.cores.core.data 0.000074 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMissRate::total 0.000074 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::processor.cores.core.data 0.000074 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::total 0.000074 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::processor.cores.core.data 34975.090909 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::total 34975.090909 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::processor.cores.core.data 34975.090909 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::total 34975.090909 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.demandMshrHits::processor.cores.core.data 22 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::total 22 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::processor.cores.core.data 22 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::total 22 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::processor.cores.core.data 11 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::total 11 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 121 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::processor.cores.core.data 11 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::total 132 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::processor.cores.core.data 518814 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::total 518814 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 1174827 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::processor.cores.core.data 518814 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::total 1693641 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::processor.cores.core.data 0.000025 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::total 0.000025 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::processor.cores.core.data 0.000025 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::total 0.000297 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 47164.909091 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::total 47164.909091 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 9709.314050 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 47164.909091 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::total 12830.613636 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 121 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::total 121 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 1174827 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::total 1174827 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 9709.314050 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::total 9709.314050 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.cores.core.data 222461 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222461 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::processor.cores.core.data 33 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::total 33 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::processor.cores.core.data 1154178 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::total 1154178 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.cores.core.data 222494 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222494 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::processor.cores.core.data 0.000148 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::total 0.000148 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::processor.cores.core.data 34975.090909 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::total 34975.090909 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::processor.cores.core.data 22 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::total 22 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::processor.cores.core.data 11 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::total 11 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::processor.cores.core.data 518814 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::total 518814 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::processor.cores.core.data 0.000049 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::total 0.000049 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.data 47164.909091 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::total 47164.909091 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.cores.core.data 222270 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222270 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.cores.core.data 222270 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222270 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 11 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 471 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 117 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy 0.248408 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage 0.914062 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 339 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 11 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 350 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 471 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 25 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 17 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 131.195836 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 806905953 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 120.235215 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.cores.core.data 10.960621 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.234834 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.cores.core.data 0.021407 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 0.256242 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1022 121 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 11 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1022::2 121 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1022 0.236328 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 0.021484 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3558244 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3558244 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.cores.core.inst 473 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 473 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.cores.core.inst 473 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 473 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::processor.cores.core.inst 24 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::total 24 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::processor.cores.core.inst 24 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::total 24 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::processor.cores.core.inst 682317 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::total 682317 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::processor.cores.core.inst 682317 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::total 682317 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.cores.core.inst 497 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 497 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.cores.core.inst 497 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 497 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissRate::processor.cores.core.inst 0.048290 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMissRate::total 0.048290 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::processor.cores.core.inst 0.048290 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::total 0.048290 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::processor.cores.core.inst 28429.875000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::total 28429.875000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::processor.cores.core.inst 28429.875000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::total 28429.875000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.demandMshrHits::processor.cores.core.inst 19 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::total 19 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::processor.cores.core.inst 19 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::total 19 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::processor.cores.core.inst 5 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::total 5 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::processor.cores.core.inst 5 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::total 5 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::processor.cores.core.inst 266400 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::total 266400 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::processor.cores.core.inst 266400 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::total 266400 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::processor.cores.core.inst 0.010060 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::total 0.010060 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::processor.cores.core.inst 0.010060 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::total 0.010060 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 53280 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::total 53280 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 53280 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::total 53280 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.cores.core.inst 473 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 473 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::processor.cores.core.inst 24 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::total 24 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::processor.cores.core.inst 682317 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::total 682317 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.cores.core.inst 497 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 497 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::processor.cores.core.inst 0.048290 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::total 0.048290 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::processor.cores.core.inst 28429.875000 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::total 28429.875000 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::processor.cores.core.inst 19 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::total 19 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::processor.cores.core.inst 5 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::total 5 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::processor.cores.core.inst 266400 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::total 266400 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::processor.cores.core.inst 0.010060 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::total 0.010060 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.inst 53280 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::total 53280 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 5 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 4.996466 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 806841684 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.cores.core.inst 4.996466 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.cores.core.inst 0.009759 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.009759 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 5 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 0.009766 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 3981 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 3981 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.demandHits::cache_hierarchy.l1d-cache-0.prefetcher 105 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::processor.cores.core.data 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::total 107 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::cache_hierarchy.l1d-cache-0.prefetcher 105 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::processor.cores.core.data 2 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::total 107 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::cache_hierarchy.l1d-cache-0.prefetcher 16 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.inst 5 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.data 9 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::total 30 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::cache_hierarchy.l1d-cache-0.prefetcher 16 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.inst 5 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.data 9 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::total 30 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.demandMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 673653 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.inst 263070 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.data 504162 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::total 1440885 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 673653 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.inst 263070 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.data 504162 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::total 1440885 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandAccesses::cache_hierarchy.l1d-cache-0.prefetcher 121 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.inst 5 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.data 11 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::total 137 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::cache_hierarchy.l1d-cache-0.prefetcher 121 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.inst 5 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.data 11 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::total 137 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.132231 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.inst 1 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.data 0.818182 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::total 0.218978 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.132231 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.inst 1 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.data 0.818182 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::total 0.218978 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 42103.312500 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.inst 52614 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.data 56018 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::total 48029.500000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 42103.312500 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.inst 52614 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.data 56018 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::total 48029.500000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.demandMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 10 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::total 10 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 10 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::total 10 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 6 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.inst 5 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.data 9 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::total 20 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 6 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l2-cache-0.prefetcher 121 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.inst 5 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.data 9 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::total 141 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 333000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.inst 261405 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.data 501165 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::total 1095570 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 333000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 5222158 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.inst 261405 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.data 501165 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::total 6317728 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.049587 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.data 0.818182 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::total 0.145985 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.049587 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.inst 1 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.data 0.818182 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::total 1.029197 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55500 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 52281 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 55685 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::total 54778.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55500 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 43158.330579 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 52281 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 55685 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::total 44806.581560 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l2-cache-0.prefetcher 121 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::total 121 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 5222158 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::total 5222158 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 43158.330579 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::total 43158.330579 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::cache_hierarchy.l1d-cache-0.prefetcher 105 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::processor.cores.core.data 2 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::total 107 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::cache_hierarchy.l1d-cache-0.prefetcher 16 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.inst 5 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.data 9 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::total 30 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::cache_hierarchy.l1d-cache-0.prefetcher 673653 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.inst 263070 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.data 504162 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::total 1440885 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::cache_hierarchy.l1d-cache-0.prefetcher 121 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.inst 5 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.data 11 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::total 137 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::cache_hierarchy.l1d-cache-0.prefetcher 0.132231 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.inst 1 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.data 0.818182 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::total 0.218978 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 42103.312500 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.inst 52614 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.data 56018 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::total 48029.500000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::cache_hierarchy.l1d-cache-0.prefetcher 10 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::total 10 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 6 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.inst 5 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.data 9 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::total 20 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 333000 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 261405 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.data 501165 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::total 1095570 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.049587 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.inst 1 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.818182 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::total 0.145985 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55500 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 52281 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 55685 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::total 54778.500000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 20 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 452 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 107 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy 0.236726 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage 0.842520 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 121 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 210 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 331 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 479 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 7 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 29 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 10 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 140.178753 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 806841018 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 5.981863 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 120.235582 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.inst 4.996479 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.data 8.964830 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.001460 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.029354 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.inst 0.001220 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.data 0.002189 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.034223 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 127 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 14 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 127 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 14 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.031006 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.003418 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 2333 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 2333 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.transDist::ReadResp 137 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::HardPFReq 127 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadSharedReq 137 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 10 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 264 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount::total 274 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 320 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 8448 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize::total 8768 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.snoops 127 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 264 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 264 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 264 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.reqLayer0.occupancy 80271 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer0.occupancy 4995 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer1.occupancy 131868 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 137 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.transDist::ReadResp 141 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 141 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 140 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 142 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::total 282 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 282 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 4480 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 4544 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::total 9024 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 9024 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 141 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 141 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 141 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 40991 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 41987 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 114385 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 141 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 4.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 60.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.inst::samples 2.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.data::samples 4.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000035986 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 206 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 70 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 70 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 70 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 60 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 6 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 4480 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 17258062.32531942 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 2738265 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 39118.07 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 3840 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.inst 128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.data 256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 986174.990018252749 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 14792624.850273789838 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.inst 493087.495009126374 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.data 986174.990018252749 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 4 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 60 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.inst 2 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.data 4 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 125298 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 1127673 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.inst 49144 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.data 100621 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 31324.50 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 18794.55 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.inst 24572.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.data 25155.25 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 3840 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.inst 128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.data 256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 4480 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores.core.inst 128 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 128 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 4 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 60 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.inst 2 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.data 4 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 70 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 986175 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 14792625 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.inst 493087 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.data 986175 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 17258062 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores.core.inst 493087 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 493087 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 986175 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 14792625 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.inst 493087 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.data 986175 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 17258062 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 70 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 35 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 32 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 178296 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 233240 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 1402736 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 2547.09 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 20039.09 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 63 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 90.00 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 7 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 640 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 403.100187 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 480.355424 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 1 14.29% 14.29% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 2 28.57% 42.86% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 4 57.14% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 7 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 4480 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 17.258062 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.09 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.09 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 90.00 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 10915.632000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 19270.288800 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 192003.168000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 8896505.973600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 78587976.230400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 110009904.429600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 423.785220 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 240313743 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 7725075 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 81104873.068800 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 108658813.082400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 418.580484 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 248038818 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 2.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 61.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.inst::samples 3.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.data::samples 5.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000041483 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 208 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 71 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 71 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 71 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 56 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 6 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 5 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 4544 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 17504606.07282399 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 2790213 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 39298.77 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 3904 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.inst 192 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.data 320 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 493087.495009126374 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 15039168.597778353840 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.inst 739631.242513689562 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.data 1232718.737522815820 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 2 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 61 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.inst 3 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.data 5 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 44338 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 1210478 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.inst 76467 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.data 155791 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 22169.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 19843.90 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.inst 25489.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.data 31158.20 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 3904 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.inst 192 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.data 320 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 4544 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores.core.inst 192 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 192 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 2 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 61 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.inst 3 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.data 5 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 71 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 493087 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 15039169 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.inst 739631 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.data 1232719 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 17504606 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores.core.inst 739631 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 739631 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 493087 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 15039169 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.inst 739631 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.data 1232719 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 17504606 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 71 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 4 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 35 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 32 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 245142 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 236572 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 1487074 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 3452.70 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 20944.70 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 65 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 91.55 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 6 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 757.333333 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 614.879721 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 413.613668 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 1 16.67% 16.67% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 1 16.67% 33.33% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 4 66.67% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 6 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 4544 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 17.504606 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.09 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.09 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 91.55 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 9356.256000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 16517.390400 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 194746.070400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 8929982.577600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 78564865.478400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 110018700.909600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 423.819107 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 240243147 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 7795671 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 81104873.068800 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 108658813.082400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 418.580484 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 248038818 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 779546 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 0.779544 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 1.282801 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 2008313 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.instsIssued 2004206 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 59 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 7453 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 19491 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.numIssuedDist::samples 779160 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 2.572265 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 1.222216 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 2180 0.28% 0.28% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 193577 24.84% 25.12% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 166281 21.34% 46.47% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 248435 31.88% 78.35% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 111927 14.37% 92.72% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 55908 7.18% 99.89% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 560 0.07% 99.96% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 182 0.02% 99.99% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 110 0.01% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 779160 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 4 1.79% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 1.79% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 219 98.21% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 222 0.01% 0.01% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 1114315 55.60% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.61% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 667286 33.29% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 222383 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 2004206 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 2.570991 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 223 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.000111 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 4787851 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 2015884 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 2003566 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 2004207 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numSquashedInsts 451 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 386 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 668749 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 222996 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 446115 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 112041 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 63 0.06% 0.06% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 48 0.04% 0.10% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 33 0.03% 0.13% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 112055 99.66% 99.79% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 111 0.10% 99.89% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.89% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 123 0.11% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 112433 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 63 5.90% 5.90% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 48 4.49% 10.39% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 33 3.09% 13.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 801 75.00% 88.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 0 0.00% 88.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 88.48% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 123 11.52% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 1068 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 1 0.64% 0.64% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.64% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 154 98.72% 99.36% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 1 0.64% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 156 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 111246 99.90% 99.90% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 111 0.10% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 111357 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 150 99.34% 99.34% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 1 0.66% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 151 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 358 0.32% 0.32% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 112030 99.64% 99.96% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 45 0.04% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 112433 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 45 28.85% 28.85% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 111 71.15% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 156 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 112055 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 111956 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 156 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 2 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.NotTakenMispredicted 45 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.cores.core.branchPred.TakenMispredicted 111 # Number branches predicted taken but are actually not taken (Count)
board.processor.cores.core.branchPred.BTBLookups 112433 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 45 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 112097 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.997012 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 4 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 156 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 156 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 63 0.06% 0.06% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 48 0.04% 0.10% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 33 0.03% 0.13% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 112055 99.66% 99.79% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 111 0.10% 99.89% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.89% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 123 0.11% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 112433 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 63 18.75% 18.75% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 1 0.30% 19.05% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 33 9.82% 28.87% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 115 34.23% 63.10% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 1 0.30% 63.39% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 63.39% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 123 36.61% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 336 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 1 2.22% 2.22% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 2.22% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 43 95.56% 97.78% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 1 2.22% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 45 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 1 2.22% 2.22% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 2.22% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 43 95.56% 97.78% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 1 2.22% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 45 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 156 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 156 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 156 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 79 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 144 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 144 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 144 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 7453 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts 154 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 778094 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 2.571387 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.668451 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 112258 14.43% 14.43% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 332514 42.73% 57.16% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 110936 14.26% 71.42% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 132 0.02% 71.44% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 8 0.00% 71.44% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 110665 14.22% 85.66% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 2 0.00% 85.66% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 2 0.00% 85.66% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 111577 14.34% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 778094 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 1112026 55.58% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 666483 33.31% 88.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 222272 11.11% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 2000781 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 111577 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 1000002 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 2000781 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 1000002 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 2000781 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 0.779544 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 1.282801 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 888755 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 2000781 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 666483 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 222272 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 1112026 55.58% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 666483 33.31% 88.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 222272 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 2000781 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 111358 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 111358 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 111247 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 111 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 111122 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 416054 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 2786 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 248921 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 272 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 111696 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 2 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 2012451 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 5 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 2003752 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 111456 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 667271 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 222355 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 2.570409 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 556290 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 889440 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 2446849 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 1558479 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 889626 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 1112805 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 112075 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 778642 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 548 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.cacheLines 497 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 19 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 779160 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 2.590700 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 3.340060 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 442893 56.84% 56.84% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 48 0.01% 56.85% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 56656 7.27% 64.12% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 4 0.00% 64.12% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 55092 7.07% 71.19% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 157 0.02% 71.21% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 55195 7.08% 78.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 45 0.01% 78.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 169070 21.70% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 779160 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 1009193 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 1.294591 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 112433 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.144229 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 244 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 272 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 794 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 2008313 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 668749 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 222996 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 119 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 88 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 2003739 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 2003566 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 1586055 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 1698455 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 2.570170 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.933822 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 444777 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 2239 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 119 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 715 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 666482 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.002795 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 0.692334 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 666470 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 202 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 666482 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses 667271 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 222355 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 497 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 1066360572 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 272 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 139122 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 1100 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 223594 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 415067 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 2011026 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 224 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 387092 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.renamedOperands 3907738 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 7368972 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 2456511 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.committedMaps 3889312 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 18259 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 968652 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads 2674751 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 4017621 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 1000002 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 2000781 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 0 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.000259 # Number of seconds simulated (Second)
simTicks 258877197 # Number of ticks simulated (Tick)
finalTick 1325237769 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 4.66 # Real time elapsed on the host (Second)
hostTickRate 55569073 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3387368 # Number of bytes of host memory used (Byte)
simInsts 2000004 # Number of instructions simulated (Count)
simOps 4001562 # Number of ops (including micro ops) simulated (Count)
hostInstRate 429294 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 858918 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.cores.core.data 444554 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 444554 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.cores.core.data 444554 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 444554 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.cores.core.data 444554 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 444554 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.cores.core.data 444554 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 444554 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.cores.core.data 222282 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 222282 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.cores.core.data 222282 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 222282 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.cores.core.data 222272 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 222272 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.cores.core.data 222272 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 222272 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 132 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 889417 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 132 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs 6738.007576 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 121 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.cores.core.data 11 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.236328 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.cores.core.data 0.021484 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 0.257812 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1022 121 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 11 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1022::2 121 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::2 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1022 0.236328 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 0.021484 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 3556432 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 3556432 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.cores.core.inst 224 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 224 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.cores.core.inst 224 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 224 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.cores.core.inst 224 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 224 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.cores.core.inst 224 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 224 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.cores.core.inst 224 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 224 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.cores.core.inst 224 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 224 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 5 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 702 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 5 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs 140.400000 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.cores.core.inst 5 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.cores.core.inst 0.009766 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.009766 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 5 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::2 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 0.009766 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 1792 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 1792 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 141 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 248 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 141 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs 1.758865 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 6 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 121 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.inst 5 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.data 9 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.001465 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.029541 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.inst 0.001221 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.data 0.002197 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.034424 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 127 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 14 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::2 127 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::2 14 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.031006 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.003418 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoops 0 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 66 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 80872677.984000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 108426617.997600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 418.834178 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 247327197 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 80872677.984000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 108426617.997600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 418.834178 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 247327197 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 66 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 80872677.984000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 108426617.997600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 418.834178 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 247327197 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 22303233.136800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 5250706.876800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 80872677.984000 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 108426617.997600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 418.834178 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 247327197 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 11550000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 777409 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 0.777407 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 1.286327 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 2006303 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.instsIssued 2002619 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 5522 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 18037 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.numIssuedDist::samples 777409 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 2.576017 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 1.215705 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 677 0.09% 0.09% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 193517 24.89% 24.98% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 166307 21.39% 46.37% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 248468 31.96% 78.33% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 111912 14.40% 92.73% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 55850 7.18% 99.91% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 561 0.07% 99.98% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 116 0.01% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 1 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 777409 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 223 100.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 0 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 1113281 55.59% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.59% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 667063 33.31% 88.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 222275 11.10% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 2002619 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 2.576017 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 223 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.000111 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 4782870 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 2011941 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 2002153 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 0 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 0 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 2002842 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numSquashedInsts 348 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.MemDepUnit__0.insertedLoads 668506 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 222836 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 446101 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 111934 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 111925 99.90% 99.90% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 112 0.10% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 112037 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 678 99.85% 99.85% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 1 0.15% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 679 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 111 100.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 111 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 111247 99.90% 99.90% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 111 0.10% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 111358 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 111 100.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 111 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 0 0.00% 0.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 112037 100.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 0 0.00% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 112037 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 0 0.00% 0.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 111 100.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 111 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 111925 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 111925 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 111 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 0 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.NotTakenMispredicted 0 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.cores.core.branchPred.TakenMispredicted 111 # Number branches predicted taken but are actually not taken (Count)
board.processor.cores.core.branchPred.BTBLookups 112037 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 112037 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 1.000000 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 0 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 0 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 0 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 0 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 111925 99.90% 99.90% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 112 0.10% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 112037 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 0 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 0 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 0 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 0 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 0 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 0 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 0 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 0 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 0 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 0 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 0 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 0 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 0 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 0 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 5522 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts 111 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 776621 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 2.576264 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.668699 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 110808 14.27% 14.27% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 332514 42.82% 57.08% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 110913 14.28% 71.36% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 114 0.01% 71.38% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 1 0.00% 71.38% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 110689 14.25% 85.63% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 2 0.00% 85.63% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 2 0.00% 85.63% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 111578 14.37% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 776621 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 0 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 1112026 55.58% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.58% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 666483 33.31% 88.89% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 222272 11.11% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 2000781 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 111578 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 1000002 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 2000781 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 1000002 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 2000781 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 0.777407 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 1.286327 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 888755 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 2000781 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 666483 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 222272 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 0 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 1112026 55.58% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.58% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 666483 33.31% 88.89% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 222272 11.11% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 2000781 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 111358 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 111358 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 111247 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 111 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 110913 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 414890 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 2471 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 248910 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 225 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 111702 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.decodedInsts 2009907 # Number of instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 2002271 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 111361 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 667056 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 222275 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 2.575570 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 556245 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 889102 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 2445704 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 1557382 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 889331 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 1112166 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 112037 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 777184 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 450 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.cacheLines 224 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.nisnDist::samples 777409 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 2.592496 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 3.340280 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 441633 56.81% 56.81% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 0 0.00% 56.81% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 56635 7.29% 64.09% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 1 0.00% 64.09% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 55067 7.08% 71.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 113 0.01% 71.19% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 55178 7.10% 78.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 0 0.00% 78.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 168782 21.71% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 777409 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 1007544 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 1.296028 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 112037 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.144116 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 225 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 563 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 2006303 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 0 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 668506 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 222836 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 116 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 0 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 111 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 2002268 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 2002153 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 1585359 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 1697617 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 2.575418 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.933873 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 444774 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 2023 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 116 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 564 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 666483 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.000005 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 0.002122 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 666483 100.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 3 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 666483 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses 667056 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 222275 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 224 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 258877197 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 225 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 138894 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 563 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 0 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 223287 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 414440 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 2008663 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 386461 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.renamedOperands 3904959 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 7363345 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 2454447 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.committedMaps 3889316 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 15649 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 0 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 0 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 968892 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads 2671346 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 4013392 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 1000002 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 2000781 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 0 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------