---------- Begin Simulation Statistics ----------
simSeconds 0.017803 # Number of seconds simulated (Second)
simTicks 17803273905 # Number of ticks simulated (Tick)
finalTick 17803273905 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 33.34 # Real time elapsed on the host (Second)
hostTickRate 533993837 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3604024 # Number of bytes of host memory used (Byte)
simInsts 26728147 # Number of instructions simulated (Count)
simOps 41096287 # Number of ops (including micro ops) simulated (Count)
hostInstRate 801685 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 1232642 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 15344269 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 15344269 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 15344269 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 15344269 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 63546 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 63546 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 63546 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 63546 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 312152202 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 312152202 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 312152202 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 312152202 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 15407815 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 15407815 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 15407815 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 15407815 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.004124 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.004124 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.004124 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.004124 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 4912.224247 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 4912.224247 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 4912.224247 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 4912.224247 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 66217 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 66217 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 2 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 2 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 2 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 2 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 63544 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 63544 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 4480 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 63544 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 68024 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 290939103 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 290939103 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 31616196 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 290939103 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 322555299 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.004124 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.004124 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.004124 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.004415 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 4578.545622 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 4578.545622 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 7057.186607 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 4578.545622 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 4741.786708 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 67768 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 4480 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 4480 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 31616196 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 31616196 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 7057.186607 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 7057.186607 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 13251710 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 13251710 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 62990 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 62990 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 302456574 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 302456574 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 13314700 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 13314700 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.004731 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.004731 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 4801.660168 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 4801.660168 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 62990 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 62990 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 281480904 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 281480904 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.004731 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.004731 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 4468.660168 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 4468.660168 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 2092559 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 2092559 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 556 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 556 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 9695628 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 9695628 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.000266 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.000266 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 17438.179856 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 17438.179856 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 2 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 2 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 554 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 554 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 9458199 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 9458199 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.000265 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.000265 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 17072.561372 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 17072.561372 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 63544 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 12168 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused 1862 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 2612 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.214661 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.039482 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 7662 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 26 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 7688 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 12168 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 568 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 404 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 255.701780 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 15412293 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 68024 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 226.571401 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 126873 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 15.819627 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 239.882153 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.061795 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.937040 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.998835 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 193 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 63 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::0 4 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 189 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 58 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.753906 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.246094 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 123330544 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 123330544 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 37073976 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 37073976 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 37073976 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 37073976 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 568 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 568 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 568 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 568 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 35603028 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 35603028 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 35603028 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 35603028 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 37074544 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 37074544 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 37074544 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 37074544 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 62681.387324 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 62681.387324 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 62681.387324 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 62681.387324 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 568 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 568 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 568 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 568 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 35413884 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 35413884 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 35413884 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 35413884 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.000015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.000015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.000015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.000015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 62348.387324 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 62348.387324 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 62348.387324 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 62348.387324 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 312 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 37073976 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 37073976 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 568 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 568 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 35603028 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 35603028 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 37074544 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 37074544 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 62681.387324 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 62681.387324 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 568 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 568 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 35413884 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 35413884 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.000015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.000015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 62348.387324 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 62348.387324 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 568 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 255.779992 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 37074544 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 568 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 65272.084507 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 61605 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 255.779992 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.999141 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.999141 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 106 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2 4 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::4 146 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 296596920 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 296596920 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.transDist::ReadResp 68038 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::WritebackDirty 66217 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::CleanEvict 1863 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::HardPFReq 2198 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExReq 554 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExResp 554 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadSharedReq 68038 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 1448 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 203816 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount::total 205264 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 36352 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 8591424 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize::total 8627776 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.snoops 2198 # Total snoops (Count)
board.cache_hierarchy.l2bus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2bus.snoopFanout::samples 70790 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::mean 0.000494 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::stdev 0.022230 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::0 70755 99.95% 99.95% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::1 35 0.05% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::total 70790 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.reqLayer0.occupancy 90361110 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer0.occupancy 567432 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer1.occupancy 67955976 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.snoop_filter.totRequests 136672 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleRequests 68080 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.totSnoops 35 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleSnoops 35 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches.prefetcher 4303 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.inst 7 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.data 63275 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::total 67585 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches.prefetcher 4303 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.inst 7 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.data 63275 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::total 67585 # number of overall hits (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches.prefetcher 177 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.inst 561 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.data 269 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::total 1007 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches.prefetcher 177 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.inst 561 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.data 269 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::total 1007 # number of overall misses (Count)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches.prefetcher 9676212 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.inst 35005293 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.data 16834149 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::total 61515654 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches.prefetcher 9676212 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.inst 35005293 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.data 16834149 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::total 61515654 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches.prefetcher 4480 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.inst 568 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.data 63544 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::total 68592 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches.prefetcher 4480 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.inst 568 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.data 63544 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::total 68592 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches.prefetcher 0.039509 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.inst 0.987676 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.data 0.004233 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::total 0.014681 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches.prefetcher 0.039509 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.inst 0.987676 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.data 0.004233 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::total 0.014681 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 54667.864407 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.inst 62398.026738 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.data 62580.479554 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::total 61088.037736 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 54667.864407 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.inst 62398.026738 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.data 62580.479554 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::total 61088.037736 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches.prefetcher 104 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::total 104 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches.prefetcher 104 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::total 104 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches.prefetcher 73 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.inst 561 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.data 269 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::total 903 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 73 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l2cache.prefetcher 1794 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.inst 561 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.data 269 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::total 2697 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 6945045 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.inst 34818480 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.data 16744572 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::total 58508097 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 6945045 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l2cache.prefetcher 103899461 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.inst 34818480 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.data 16744572 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::total 162407558 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.016295 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.inst 0.987676 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.data 0.004233 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::total 0.013165 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.016295 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.inst 0.987676 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.data 0.004233 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::total 0.039319 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 95137.602740 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 62065.026738 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 62247.479554 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::total 64793.019934 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 95137.602740 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 57914.972687 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 62065.026738 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 62247.479554 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::total 60217.856136 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::cache_hierarchy.l2cache.prefetcher 1794 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::total 1794 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.l2cache.prefetcher 103899461 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::total 103899461 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 57914.972687 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::total 57914.972687 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores.core.data 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::total 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores.core.data 119 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::total 119 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores.core.data 7489836 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::total 7489836 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores.core.data 554 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::total 554 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores.core.data 0.214801 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::total 0.214801 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 62939.798319 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::total 62939.798319 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 119 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::total 119 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 7450209 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::total 7450209 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.214801 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::total 0.214801 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 62606.798319 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::total 62606.798319 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches.prefetcher 4303 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.inst 7 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.data 62840 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::total 67150 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::cache_hierarchy.l1dcaches.prefetcher 177 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.inst 561 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.data 150 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::total 888 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::cache_hierarchy.l1dcaches.prefetcher 9676212 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 35005293 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 9344313 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::total 54025818 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::cache_hierarchy.l1dcaches.prefetcher 4480 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 568 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.data 62990 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::total 68038 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::cache_hierarchy.l1dcaches.prefetcher 0.039509 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.987676 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.data 0.002381 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::total 0.013052 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches.prefetcher 54667.864407 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 62398.026738 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 62295.420000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::total 60839.885135 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.l1dcaches.prefetcher 104 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::total 104 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 73 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 561 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 150 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::total 784 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 6945045 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 34818480 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 9294363 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::total 51057888 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.016295 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.987676 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.002381 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::total 0.011523 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 95137.602740 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 62065.026738 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 61962.420000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::total 65124.857143 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.WritebackDirty.hits::writebacks 66217 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.hits::total 66217 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::writebacks 66217 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::total 66217 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.prefetcher.demandMshrMisses 903 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIssued 6791 # number of hwpf issued (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUseful 1686 # number of useful prefetch (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2cache.prefetcher.accuracy 0.248270 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.coverage 0.651217 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInCache 4894 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInMSHR 103 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2cache.prefetcher.pfLate 4997 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIdentified 7276 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2cache.prefetcher.pfBufferHit 278 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedDemand 104 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2cache.prefetcher.pfSpanPage 352 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulSpanPage 263 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.tags.tagsInUse 2249.263066 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2cache.tags.totalRefs 138362 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.sampledRefs 2697 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.avgRefs 51.302188 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2cache.tags.warmupTick 60939 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 91.702368 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l2cache.prefetcher 1466.935730 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.inst 452.347312 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.data 238.277656 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.022388 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l2cache.prefetcher 0.358139 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.inst 0.110436 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.data 0.058173 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::total 0.549136 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1022 1867 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1024 830 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::2 22 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::3 313 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::4 1532 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::0 127 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::2 7 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::3 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::4 691 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1022 0.455811 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1024 0.202637 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.tagAccesses 2189449 # Number of tag accesses (Count)
board.cache_hierarchy.l2cache.tags.dataAccesses 2189449 # Number of data accesses (Count)
board.cache_hierarchy.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 2578 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 119 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 119 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 2578 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.module.port 5394 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::total 5394 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 5394 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.module.port 172608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::total 172608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 172608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 3009 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 3009 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 3009 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 1568379 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 2231595 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 3009 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.module.bytesRead::cache_hierarchy.l1dcaches.prefetcher 6912 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::cache_hierarchy.l2cache.prefetcher 112576 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores.core.inst 35904 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::processor.cores.core.data 17216 # Number of bytes read from this memory (Byte)
board.memory.module.bytesRead::total 172608 # Number of bytes read from this memory (Byte)
board.memory.module.bytesInstRead::processor.cores.core.inst 35904 # Number of instructions bytes read from this memory (Byte)
board.memory.module.bytesInstRead::total 35904 # Number of instructions bytes read from this memory (Byte)
board.memory.module.numReads::cache_hierarchy.l1dcaches.prefetcher 108 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::cache_hierarchy.l2cache.prefetcher 1759 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores.core.inst 561 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::processor.cores.core.data 269 # Number of read requests responded to by this memory (Count)
board.memory.module.numReads::total 2697 # Number of read requests responded to by this memory (Count)
board.memory.module.bwRead::cache_hierarchy.l1dcaches.prefetcher 388243 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::cache_hierarchy.l2cache.prefetcher 6323331 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores.core.inst 2016708 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::processor.cores.core.data 967013 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwRead::total 9695295 # Total read bandwidth from this memory ((Byte/Second))
board.memory.module.bwInstRead::processor.cores.core.inst 2016708 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.module.bwInstRead::total 2016708 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l1dcaches.prefetcher 388243 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::cache_hierarchy.l2cache.prefetcher 6323331 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores.core.inst 2016708 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::processor.cores.core.data 967013 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.bwTotal::total 9695295 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.module.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 53463285 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 2.000260 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.499935 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.commitStats0.numInsts 26728168 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 41096338 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 2.000260 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.499935 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 1372 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 41095270 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 13314722 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2093120 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 341 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 22647397 55.11% 55.11% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3040040 7.40% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 56 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 146 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 160 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 86 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 270 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 13314634 32.40% 94.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2092647 5.09% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 88 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 41096338 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1054261 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1053819 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 442 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1043154 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 11107 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 263 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 259 # Class of control type instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns 522 # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles 0.003003 # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 53463284.996997 # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction 1.000000 # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction 0.000000 # Percentage of idle cycles (Ratio)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 15407842 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpAluAccesses 1372 # Number of float alu accesses (Count)
board.processor.cores.core.executeStats0.numFpRegReads 1683 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 817 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntAluAccesses 41095270 # Number of integer alu accesses (Count)
board.processor.cores.core.executeStats0.numIntRegReads 61498641 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 36904843 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 15407842 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 17516410 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetchStats0.numInsts 26728168 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 41096338 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.499935 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1054261 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.019719 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.mmu.dtb.rdAccesses 13314728 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 2093120 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 68 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 15 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 37074544 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 49 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 17803273905 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 18 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------