---------- Begin Simulation Statistics ----------
simSeconds 0.020000 # Number of seconds simulated (Second)
simTicks 20000000000 # Number of ticks simulated (Tick)
finalTick 20000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 14.00 # Real time elapsed on the host (Second)
hostTickRate 1428234773 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 2173216 # Number of bytes of host memory used (Byte)
simInsts 10698810 # Number of instructions simulated (Count)
simOps 11227637 # Number of ops (including micro ops) simulated (Count)
hostInstRate 764014 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 801777 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.demandHits::processor.cores.core.mmu.dtb_walker 92 # number of demand (read+write) hits (Count)
board.cache_hierarchy.dptw_caches.demandHits::total 92 # number of demand (read+write) hits (Count)
board.cache_hierarchy.dptw_caches.overallHits::processor.cores.core.mmu.dtb_walker 92 # number of overall hits (Count)
board.cache_hierarchy.dptw_caches.overallHits::total 92 # number of overall hits (Count)
board.cache_hierarchy.dptw_caches.demandMisses::processor.cores.core.mmu.dtb_walker 16782 # number of demand (read+write) misses (Count)
board.cache_hierarchy.dptw_caches.demandMisses::total 16782 # number of demand (read+write) misses (Count)
board.cache_hierarchy.dptw_caches.overallMisses::processor.cores.core.mmu.dtb_walker 16782 # number of overall misses (Count)
board.cache_hierarchy.dptw_caches.overallMisses::total 16782 # number of overall misses (Count)
board.cache_hierarchy.dptw_caches.demandMissLatency::processor.cores.core.mmu.dtb_walker 235882218 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.dptw_caches.demandMissLatency::total 235882218 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.dptw_caches.overallMissLatency::processor.cores.core.mmu.dtb_walker 235882218 # number of overall miss ticks (Tick)
board.cache_hierarchy.dptw_caches.overallMissLatency::total 235882218 # number of overall miss ticks (Tick)
board.cache_hierarchy.dptw_caches.demandAccesses::processor.cores.core.mmu.dtb_walker 16874 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.dptw_caches.demandAccesses::total 16874 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.dptw_caches.overallAccesses::processor.cores.core.mmu.dtb_walker 16874 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.dptw_caches.overallAccesses::total 16874 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.dptw_caches.demandMissRate::processor.cores.core.mmu.dtb_walker 0.994548 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.dptw_caches.demandMissRate::total 0.994548 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.dptw_caches.overallMissRate::processor.cores.core.mmu.dtb_walker 0.994548 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.dptw_caches.overallMissRate::total 0.994548 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.dptw_caches.demandAvgMissLatency::processor.cores.core.mmu.dtb_walker 14055.667858 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.dptw_caches.demandAvgMissLatency::total 14055.667858 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.dptw_caches.overallAvgMissLatency::processor.cores.core.mmu.dtb_walker 14055.667858 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.overallAvgMissLatency::total 14055.667858 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.writebacks::writebacks 3 # number of writebacks (Count)
board.cache_hierarchy.dptw_caches.writebacks::total 3 # number of writebacks (Count)
board.cache_hierarchy.dptw_caches.demandMshrMisses::processor.cores.core.mmu.dtb_walker 16782 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.dptw_caches.demandMshrMisses::total 16782 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.dptw_caches.overallMshrMisses::processor.cores.core.mmu.dtb_walker 16782 # number of overall MSHR misses (Count)
board.cache_hierarchy.dptw_caches.overallMshrMisses::total 16782 # number of overall MSHR misses (Count)
board.cache_hierarchy.dptw_caches.demandMshrMissLatency::processor.cores.core.mmu.dtb_walker 219100218 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.demandMshrMissLatency::total 219100218 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.overallMshrMissLatency::processor.cores.core.mmu.dtb_walker 219100218 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.overallMshrMissLatency::total 219100218 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.demandMshrMissRate::processor.cores.core.mmu.dtb_walker 0.994548 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.dptw_caches.demandMshrMissRate::total 0.994548 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.dptw_caches.overallMshrMissRate::processor.cores.core.mmu.dtb_walker 0.994548 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.dptw_caches.overallMshrMissRate::total 0.994548 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.dptw_caches.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb_walker 13055.667858 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.demandAvgMshrMissLatency::total 13055.667858 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb_walker 13055.667858 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.overallAvgMshrMissLatency::total 13055.667858 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.replacements 3 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.ReadReq.hits::processor.cores.core.mmu.dtb_walker 92 # number of ReadReq hits (Count)
board.cache_hierarchy.dptw_caches.ReadReq.hits::total 92 # number of ReadReq hits (Count)
board.cache_hierarchy.dptw_caches.ReadReq.misses::processor.cores.core.mmu.dtb_walker 16782 # number of ReadReq misses (Count)
board.cache_hierarchy.dptw_caches.ReadReq.misses::total 16782 # number of ReadReq misses (Count)
board.cache_hierarchy.dptw_caches.ReadReq.missLatency::processor.cores.core.mmu.dtb_walker 235882218 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.dptw_caches.ReadReq.missLatency::total 235882218 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.dptw_caches.ReadReq.accesses::processor.cores.core.mmu.dtb_walker 16874 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.dptw_caches.ReadReq.accesses::total 16874 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.dptw_caches.ReadReq.missRate::processor.cores.core.mmu.dtb_walker 0.994548 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.dptw_caches.ReadReq.missRate::total 0.994548 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.dptw_caches.ReadReq.avgMissLatency::processor.cores.core.mmu.dtb_walker 14055.667858 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.ReadReq.avgMissLatency::total 14055.667858 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.ReadReq.mshrMisses::processor.cores.core.mmu.dtb_walker 16782 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.dptw_caches.ReadReq.mshrMisses::total 16782 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.dptw_caches.ReadReq.mshrMissLatency::processor.cores.core.mmu.dtb_walker 219100218 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.ReadReq.mshrMissLatency::total 219100218 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.dptw_caches.ReadReq.mshrMissRate::processor.cores.core.mmu.dtb_walker 0.994548 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.dptw_caches.ReadReq.mshrMissRate::total 0.994548 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.dptw_caches.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.dtb_walker 13055.667858 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.ReadReq.avgMshrMissLatency::total 13055.667858 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 10.046079 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 16874 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 16782 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs 1.005482 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 105931000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.occupancies::processor.cores.core.mmu.dtb_walker 10.046079 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.dptw_caches.tags.avgOccs::processor.cores.core.mmu.dtb_walker 0.078485 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.dptw_caches.tags.avgOccs::total 0.078485 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.dptw_caches.tags.occupanciesTaskId::1023 24 # Occupied blocks per task id (Count)
board.cache_hierarchy.dptw_caches.tags.ageTaskId_1023::2 15 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.dptw_caches.tags.ageTaskId_1023::3 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.dptw_caches.tags.ageTaskId_1023::4 8 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.dptw_caches.tags.ratioOccsTaskId::1023 0.187500 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 84278 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 84278 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iocache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iocache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iocache.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iocache.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.demandHits::processor.cores.core.mmu.itb_walker 57 # number of demand (read+write) hits (Count)
board.cache_hierarchy.iptw_caches.demandHits::total 57 # number of demand (read+write) hits (Count)
board.cache_hierarchy.iptw_caches.overallHits::processor.cores.core.mmu.itb_walker 57 # number of overall hits (Count)
board.cache_hierarchy.iptw_caches.overallHits::total 57 # number of overall hits (Count)
board.cache_hierarchy.iptw_caches.demandMisses::processor.cores.core.mmu.itb_walker 23 # number of demand (read+write) misses (Count)
board.cache_hierarchy.iptw_caches.demandMisses::total 23 # number of demand (read+write) misses (Count)
board.cache_hierarchy.iptw_caches.overallMisses::processor.cores.core.mmu.itb_walker 23 # number of overall misses (Count)
board.cache_hierarchy.iptw_caches.overallMisses::total 23 # number of overall misses (Count)
board.cache_hierarchy.iptw_caches.demandMissLatency::processor.cores.core.mmu.itb_walker 1373977 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.iptw_caches.demandMissLatency::total 1373977 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.iptw_caches.overallMissLatency::processor.cores.core.mmu.itb_walker 1373977 # number of overall miss ticks (Tick)
board.cache_hierarchy.iptw_caches.overallMissLatency::total 1373977 # number of overall miss ticks (Tick)
board.cache_hierarchy.iptw_caches.demandAccesses::processor.cores.core.mmu.itb_walker 80 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.iptw_caches.demandAccesses::total 80 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.iptw_caches.overallAccesses::processor.cores.core.mmu.itb_walker 80 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.iptw_caches.overallAccesses::total 80 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.iptw_caches.demandMissRate::processor.cores.core.mmu.itb_walker 0.287500 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.iptw_caches.demandMissRate::total 0.287500 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.iptw_caches.overallMissRate::processor.cores.core.mmu.itb_walker 0.287500 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.iptw_caches.overallMissRate::total 0.287500 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.iptw_caches.demandAvgMissLatency::processor.cores.core.mmu.itb_walker 59738.130435 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.iptw_caches.demandAvgMissLatency::total 59738.130435 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.iptw_caches.overallAvgMissLatency::processor.cores.core.mmu.itb_walker 59738.130435 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.overallAvgMissLatency::total 59738.130435 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.writebacks::writebacks 6 # number of writebacks (Count)
board.cache_hierarchy.iptw_caches.writebacks::total 6 # number of writebacks (Count)
board.cache_hierarchy.iptw_caches.demandMshrMisses::processor.cores.core.mmu.itb_walker 23 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.iptw_caches.demandMshrMisses::total 23 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.iptw_caches.overallMshrMisses::processor.cores.core.mmu.itb_walker 23 # number of overall MSHR misses (Count)
board.cache_hierarchy.iptw_caches.overallMshrMisses::total 23 # number of overall MSHR misses (Count)
board.cache_hierarchy.iptw_caches.demandMshrMissLatency::processor.cores.core.mmu.itb_walker 1350977 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.demandMshrMissLatency::total 1350977 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.overallMshrMissLatency::processor.cores.core.mmu.itb_walker 1350977 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.overallMshrMissLatency::total 1350977 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.demandMshrMissRate::processor.cores.core.mmu.itb_walker 0.287500 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.iptw_caches.demandMshrMissRate::total 0.287500 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.iptw_caches.overallMshrMissRate::processor.cores.core.mmu.itb_walker 0.287500 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.iptw_caches.overallMshrMissRate::total 0.287500 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.iptw_caches.demandAvgMshrMissLatency::processor.cores.core.mmu.itb_walker 58738.130435 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.demandAvgMshrMissLatency::total 58738.130435 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.overallAvgMshrMissLatency::processor.cores.core.mmu.itb_walker 58738.130435 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.overallAvgMshrMissLatency::total 58738.130435 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.replacements 6 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.ReadReq.hits::processor.cores.core.mmu.itb_walker 57 # number of ReadReq hits (Count)
board.cache_hierarchy.iptw_caches.ReadReq.hits::total 57 # number of ReadReq hits (Count)
board.cache_hierarchy.iptw_caches.ReadReq.misses::processor.cores.core.mmu.itb_walker 23 # number of ReadReq misses (Count)
board.cache_hierarchy.iptw_caches.ReadReq.misses::total 23 # number of ReadReq misses (Count)
board.cache_hierarchy.iptw_caches.ReadReq.missLatency::processor.cores.core.mmu.itb_walker 1373977 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.iptw_caches.ReadReq.missLatency::total 1373977 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.iptw_caches.ReadReq.accesses::processor.cores.core.mmu.itb_walker 80 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.iptw_caches.ReadReq.accesses::total 80 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.iptw_caches.ReadReq.missRate::processor.cores.core.mmu.itb_walker 0.287500 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.iptw_caches.ReadReq.missRate::total 0.287500 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.iptw_caches.ReadReq.avgMissLatency::processor.cores.core.mmu.itb_walker 59738.130435 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.ReadReq.avgMissLatency::total 59738.130435 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.ReadReq.mshrMisses::processor.cores.core.mmu.itb_walker 23 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.iptw_caches.ReadReq.mshrMisses::total 23 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.iptw_caches.ReadReq.mshrMissLatency::processor.cores.core.mmu.itb_walker 1350977 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.ReadReq.mshrMissLatency::total 1350977 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.iptw_caches.ReadReq.mshrMissRate::processor.cores.core.mmu.itb_walker 0.287500 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.iptw_caches.ReadReq.mshrMissRate::total 0.287500 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.iptw_caches.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.itb_walker 58738.130435 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.ReadReq.avgMshrMissLatency::total 58738.130435 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 4.585408 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 80 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 23 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs 3.478261 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 105589000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.occupancies::processor.cores.core.mmu.itb_walker 4.585408 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.iptw_caches.tags.avgOccs::processor.cores.core.mmu.itb_walker 0.035823 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.iptw_caches.tags.avgOccs::total 0.035823 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.iptw_caches.tags.occupanciesTaskId::1023 17 # Occupied blocks per task id (Count)
board.cache_hierarchy.iptw_caches.tags.ageTaskId_1023::2 15 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.iptw_caches.tags.ageTaskId_1023::3 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.iptw_caches.tags.ageTaskId_1023::4 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.iptw_caches.tags.ratioOccsTaskId::1023 0.132812 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 343 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 343 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 2298756 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 2298756 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 2298843 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 2298843 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 156080 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 156080 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 156088 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 156088 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 6649880000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 6649880000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 6649880000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 6649880000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 2454836 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 2454836 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 2454931 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 2454931 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.063581 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.063581 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.063581 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.063581 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 42605.586879 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 42605.586879 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 42603.403208 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 42603.403208 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 140713 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 140713 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 39055 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 39055 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 39055 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 39055 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 117025 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 117025 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 183990 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 117033 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 301023 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrUncacheable::processor.cores.core.data 62 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrUncacheable::total 62 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 5934852000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 5934852000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 11874583063 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 5935258000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 17809841063 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrUncacheableLatency::processor.cores.core.data 579000 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrUncacheableLatency::total 579000 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.047671 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.047671 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.047673 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.122620 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 50714.394360 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 50714.394360 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 64539.285086 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 50714.396794 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 59164.386319 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrUncacheableLatency::processor.cores.core.data 9338.709677 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrUncacheableLatency::total 9338.709677 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 283242 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.missLatency::processor.cores.core.data 40000 # number of CleanInvalidReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.missLatency::total 40000 # number of CleanInvalidReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.avgMissLatency::processor.cores.core.data inf # average CleanInvalidReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.CleanInvalidReq.avgMissLatency::total inf # average CleanInvalidReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMisses::processor.cores.core.data 8 # number of CleanInvalidReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMisses::total 8 # number of CleanInvalidReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMissLatency::processor.cores.core.data 72000 # number of CleanInvalidReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMissLatency::total 72000 # number of CleanInvalidReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMissRate::processor.cores.core.data inf # mshr miss rate for CleanInvalidReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.mshrMissRate::total inf # mshr miss rate for CleanInvalidReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.CleanInvalidReq.avgMshrMissLatency::processor.cores.core.data 9000 # average CleanInvalidReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.CleanInvalidReq.avgMshrMissLatency::total 9000 # average CleanInvalidReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 183990 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 183990 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 11874583063 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 11874583063 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 64539.285086 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 64539.285086 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMisses::processor.cores.core.data 321 # number of InvalidateReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMisses::total 321 # number of InvalidateReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMissLatency::processor.cores.core.data 2889000 # number of InvalidateReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMissLatency::total 2889000 # number of InvalidateReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMissRate::processor.cores.core.data inf # mshr miss rate for InvalidateReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.InvalidateReq.mshrMissRate::total inf # mshr miss rate for InvalidateReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.InvalidateReq.avgMshrMissLatency::processor.cores.core.data 9000 # average InvalidateReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.InvalidateReq.avgMshrMissLatency::total 9000 # average InvalidateReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::processor.cores.core.data 124 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::total 124 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::processor.cores.core.data 10 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::total 10 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missLatency::processor.cores.core.data 554000 # number of LoadLockedReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missLatency::total 554000 # number of LoadLockedReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::processor.cores.core.data 134 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::total 134 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::processor.cores.core.data 0.074627 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::total 0.074627 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMissLatency::processor.cores.core.data 55400 # average LoadLockedReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMissLatency::total 55400 # average LoadLockedReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrHits::processor.cores.core.data 8 # number of LoadLockedReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrHits::total 8 # number of LoadLockedReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMisses::processor.cores.core.data 2 # number of LoadLockedReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMisses::total 2 # number of LoadLockedReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissLatency::processor.cores.core.data 154000 # number of LoadLockedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissLatency::total 154000 # number of LoadLockedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissRate::processor.cores.core.data 0.014925 # mshr miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.mshrMissRate::total 0.014925 # mshr miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMshrMissLatency::processor.cores.core.data 77000 # average LoadLockedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.LoadLockedReq.avgMshrMissLatency::total 77000 # average LoadLockedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 1563361 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 1563361 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 87290 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 87290 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 5141916000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 5141916000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 1650651 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 1650651 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.052882 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.052882 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 58906.128995 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 58906.128995 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 87290 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 87290 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrUncacheable::processor.cores.core.data 19 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrUncacheable::total 19 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 5054626000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 5054626000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrUncacheableLatency::processor.cores.core.data 579000 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrUncacheableLatency::total 579000 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.052882 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.052882 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 57906.128995 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 57906.128995 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 30473.684211 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrUncacheableLatency::total 30473.684211 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.SoftPFExReq.hits::processor.cores.core.data 87 # number of SoftPFExReq hits (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.hits::total 87 # number of SoftPFExReq hits (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.misses::processor.cores.core.data 8 # number of SoftPFExReq misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.misses::total 8 # number of SoftPFExReq misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.accesses::processor.cores.core.data 95 # number of SoftPFExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.accesses::total 95 # number of SoftPFExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.missRate::processor.cores.core.data 0.084211 # miss rate for SoftPFExReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFExReq.missRate::total 0.084211 # miss rate for SoftPFExReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMisses::processor.cores.core.data 8 # number of SoftPFExReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMisses::total 8 # number of SoftPFExReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMissLatency::processor.cores.core.data 406000 # number of SoftPFExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMissLatency::total 406000 # number of SoftPFExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMissRate::processor.cores.core.data 0.084211 # mshr miss rate for SoftPFExReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFExReq.mshrMissRate::total 0.084211 # mshr miss rate for SoftPFExReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SoftPFExReq.avgMshrMissLatency::processor.cores.core.data 50750 # average SoftPFExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.SoftPFExReq.avgMshrMissLatency::total 50750 # average SoftPFExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::processor.cores.core.data 129 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::total 129 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::processor.cores.core.data 129 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::total 129 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.hits::processor.cores.core.data 4950 # number of WriteLineReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.hits::total 4950 # number of WriteLineReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.misses::processor.cores.core.data 38033 # number of WriteLineReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.misses::total 38033 # number of WriteLineReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.missLatency::processor.cores.core.data 550931000 # number of WriteLineReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteLineReq.missLatency::total 550931000 # number of WriteLineReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteLineReq.accesses::processor.cores.core.data 42983 # number of WriteLineReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.accesses::total 42983 # number of WriteLineReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.missRate::processor.cores.core.data 0.884838 # miss rate for WriteLineReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteLineReq.missRate::total 0.884838 # miss rate for WriteLineReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteLineReq.avgMissLatency::processor.cores.core.data 14485.604607 # average WriteLineReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteLineReq.avgMissLatency::total 14485.604607 # average WriteLineReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrHits::processor.cores.core.data 37351 # number of WriteLineReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrHits::total 37351 # number of WriteLineReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMisses::processor.cores.core.data 682 # number of WriteLineReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMisses::total 682 # number of WriteLineReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMissLatency::processor.cores.core.data 6138000 # number of WriteLineReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMissLatency::total 6138000 # number of WriteLineReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMissRate::processor.cores.core.data 0.015867 # mshr miss rate for WriteLineReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteLineReq.mshrMissRate::total 0.015867 # mshr miss rate for WriteLineReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteLineReq.avgMshrMissLatency::processor.cores.core.data 9000 # average WriteLineReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteLineReq.avgMshrMissLatency::total 9000 # average WriteLineReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 730445 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 730445 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 30757 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 30757 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 957033000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 957033000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 761202 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 761202 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.040406 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.040406 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 31115.941087 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 31115.941087 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 1704 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 1704 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 29053 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 29053 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrUncacheable::processor.cores.core.data 43 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrUncacheable::total 43 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 874088000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 874088000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.038167 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.038167 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 30085.980794 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 30085.980794 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 117025 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 655654 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused 15360 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 129567 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.197615 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.525431 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 316511 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 155153 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 471664 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 655654 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 41466 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 33882 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 1016.953433 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 2600125 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 284270 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 9.146674 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 106098000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 741.944710 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 275.008723 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.724555 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.268563 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.993119 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 886 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 138 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::2 886 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 26 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::2 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::3 19 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::4 3 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.865234 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.134766 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 19928454 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 19928454 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 10696015 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 10696015 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 10696015 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 10696015 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 860 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 860 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 860 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 860 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 49545000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 49545000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 49545000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 49545000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 10696875 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 10696875 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 10696875 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 10696875 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000080 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000080 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000080 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000080 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 57610.465116 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 57610.465116 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 57610.465116 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 57610.465116 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks 63 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total 63 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 860 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 860 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 860 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 860 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrUncacheable::processor.cores.core.inst 1938 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1icaches.overallMshrUncacheable::total 1938 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 48685000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 48685000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 48685000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 48685000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrUncacheableLatency::processor.cores.core.inst 100443000 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrUncacheableLatency::total 100443000 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.000080 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.000080 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.000080 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.000080 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 56610.465116 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 56610.465116 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 56610.465116 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 56610.465116 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrUncacheableLatency::processor.cores.core.inst 51828.173375 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrUncacheableLatency::total 51828.173375 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 63 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 10696015 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 10696015 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 860 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 860 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 49545000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 49545000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 10696875 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 10696875 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000080 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000080 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 57610.465116 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 57610.465116 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 860 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 860 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrUncacheable::processor.cores.core.inst 1938 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrUncacheable::total 1938 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 48685000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 48685000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrUncacheableLatency::processor.cores.core.inst 100443000 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrUncacheableLatency::total 100443000 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.000080 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.000080 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 56610.465116 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 56610.465116 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrUncacheableLatency::processor.cores.core.inst 51828.173375 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrUncacheableLatency::total 51828.173375 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 860 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 397.273510 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 10696875 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 860 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 12438.226744 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 105755000 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 397.273510 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.387962 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.387962 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 796 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2 71 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::3 619 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::4 106 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 0.777344 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 85575860 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 85575860 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadReq 1957 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadResp 290904 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteReq 43 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteResp 43 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 140713 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean 72 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteClean 4 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 142529 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::UpgradeReq 16755 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 12306 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 12306 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 288947 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanInvalidReq 8 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::InvalidateReq 1003 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.realview.bootmem.port 168 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 5491 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total 5659 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.iobridge.cpu_side_port 8 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.realview.bootmem.port 18 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.realview.gic.pio 20 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 868266 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total 868312 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.iptw_caches.mem_side_port::board.memory.mem_ctrl.port 52 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.iptw_caches.mem_side_port::total 52 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.dptw_caches.mem_side_port::board.memory.mem_ctrl.port 16805 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.dptw_caches.mem_side_port::total 16805 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 890828 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.realview.bootmem.port 336 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 66488 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total 66824 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.iobridge.cpu_side_port 16 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.realview.bootmem.port 68 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.realview.gic.pio 40 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 27155832 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total 27155956 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.iptw_caches.mem_side_port::board.memory.mem_ctrl.port 1856 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.iptw_caches.mem_side_port::total 1856 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.dptw_caches.mem_side_port::board.memory.mem_ctrl.port 1472 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.dptw_caches.mem_side_port::total 1472 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 27226108 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 16762 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 1072768 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 321019 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0.104455 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0.305850 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 287487 89.55% 89.55% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 33532 10.45% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::5 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 321019 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 8000 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 93000 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer12.occupancy 16000 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer12.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer13.occupancy 873392527 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer13.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 6919460 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer3.occupancy 705849660 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer3.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer4.occupancy 55444 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer4.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer5.occupancy 33573000 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer5.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 602333 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 283325 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 33526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 1000 # Clock period in ticks (Tick)
board.iobridge.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.transDist::WriteReq 4 # Transaction distribution (Count)
board.iobus.transDist::WriteResp 4 # Transaction distribution (Count)
board.iobus.pktCount_board.iobridge.mem_side_port::board.realview.realview_io.pio 4 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.iobridge.mem_side_port::board.realview.uart0.pio 4 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.iobridge.mem_side_port::total 8 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount::total 8 # Packet count per connected requestor and responder (Count)
board.iobus.pktSize_board.iobridge.mem_side_port::board.realview.realview_io.pio 8 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.iobridge.mem_side_port::board.realview.uart0.pio 8 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.iobridge.mem_side_port::total 16 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize::total 16 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.reqLayer12.occupancy 4000 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer12.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer2.utilization 0.0 # Layer utilization (Ratio)
board.iobus.respLayer0.occupancy 4000 # Layer occupancy (ticks) (Tick)
board.iobus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.memory.mem_ctrl.avgPriority_writebacks::samples 140783.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 183990.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.dtb_walker::samples 20.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.itb_walker::samples 23.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 2714.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 99573.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.001738989652 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 8441 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 8441 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 673268 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 132437 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 286351 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 140816 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 286351 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 140816 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 37 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 27 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 2.32 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 58.58 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 1854 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 6 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 284491 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 33 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 140783 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 148010 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 77247 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 25259 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 23921 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 9968 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 1564 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 268 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 58 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 16 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 1924 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 2453 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 5610 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 6763 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 7224 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 7715 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 9726 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 9629 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 9401 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 9071 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 9577 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 9860 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 9242 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 8572 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 8459 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 8454 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 8509 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::64 8519 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::65 19 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::66 10 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::67 5 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples 8441 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean 33.918138 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean 27.904611 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev 118.018613 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::0-255 8435 99.93% 99.93% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::256-511 4 0.05% 99.98% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::2816-3071 1 0.01% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::10240-10495 1 0.01% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total 8441 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples 8441 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean 16.672314 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean 16.635496 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev 1.143891 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16 5968 70.70% 70.70% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17 329 3.90% 74.60% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18 1346 15.95% 90.55% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19 599 7.10% 97.64% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::20 148 1.75% 99.40% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::21 42 0.50% 99.89% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::22 8 0.09% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total 8441 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ 2368 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 18214888 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 9010376 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 910744400.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 450518800.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 19992615000 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 46802.81 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 11775360 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.dtb_walker 1280 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.itb_walker 1472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 62456 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 6372288 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks 9006400 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::processor.cores.core.data 48 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 588768000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.dtb_walker 64000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.itb_walker 73600.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 3122800.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 318614400.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 450320000.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::processor.cores.core.data 2400.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 183990 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.dtb_walker 20 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.itb_walker 23 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 2714 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 99604 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks 140783 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::processor.cores.core.data 33 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 6060716670 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.dtb_walker 556000 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.itb_walker 600556 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 60216540 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 2626342614 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks 1152369110593 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::processor.cores.core.data 883174190 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 32940.47 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.dtb_walker 27800.00 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.itb_walker 26111.13 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 22187.38 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 26367.84 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks 8185428.00 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::processor.cores.core.data 26762854.24 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 11775360 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.dtb_walker 1280 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.itb_walker 1472 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 62456 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 6374320 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 18214888 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 62456 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 62456 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks 9005888 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::processor.cores.core.data 264 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total 9006152 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 183990 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.dtb_walker 20 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.itb_walker 23 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 2714 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 99604 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 286351 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks 140717 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::processor.cores.core.data 33 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total 140750 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 588768000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.dtb_walker 64000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.itb_walker 73600 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 3122800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 318716000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 910744400 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 3122800 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 3122800 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks 450294400 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::processor.cores.core.data 13200 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total 450307600 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks 450294400 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 588768000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.dtb_walker 64000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.itb_walker 73600 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 3122800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 318729200 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 1361052000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 286314 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 140731 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 9333 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 8622 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 8448 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 8862 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 8956 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 8997 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 8813 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 9324 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 9054 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 9350 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 9241 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 8951 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 9562 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 9448 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 9209 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 9137 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 9102 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 9216 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 9171 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 8719 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 8970 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 8761 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 8404 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 8389 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 8149 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 9627 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 8584 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 8811 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 8676 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 8473 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 9012 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 8943 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 4480 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 4097 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 4089 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 4309 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 4420 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 4522 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 4339 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 4771 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 4662 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 4846 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 4801 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 4504 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 4718 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 4916 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 4711 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 4556 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 4631 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 4585 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 4655 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 4243 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 4464 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 4138 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 4023 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 4057 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 3865 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 4044 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 3941 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 4238 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 4269 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 4095 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 4345 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 4397 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 3740227892 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 953998248 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 8748432380 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 13063.38 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 30555.38 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 262909 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 128644 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 91.83 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate 91.41 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 35491 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 770.077372 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 597.086796 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 361.346342 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 3138 8.84% 8.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 2670 7.52% 16.36% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 1588 4.47% 20.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 1463 4.12% 24.96% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 1570 4.42% 29.38% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 1320 3.72% 33.10% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 1172 3.30% 36.41% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 1562 4.40% 40.81% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 21008 59.19% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 35491 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 18324096 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 9006784 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 916.204800 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 450.339200 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 7.11 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 4.77 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 2.34 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 91.69 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 28092158.640000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 49590711.777600 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 398562919.036795 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 171600092.495998 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 1735597051.372696 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 5192331162.429703 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 2943446550.240027 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 10519220645.992832 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 525.961032 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 8933795816 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 898800000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 10167404184 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 27253214.352000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 48112405.336800 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 386768438.716797 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 160392217.439999 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 1735597051.372696 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 5102958475.809702 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 3005145460.800029 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 10466227263.828035 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 523.311363 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 9114909511 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 898800000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 9986290489 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pci_devices.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 20000000 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.869366 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.534941 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.commitStats0.numInsts 10698812 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 11227639 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.869366 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.534941 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 8696752 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 1608384 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 804683 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 5463 0.05% 0.05% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 8805048 78.42% 78.47% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 4061 0.04% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 78.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 1608384 14.33% 92.83% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 804683 7.17% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 11227639 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 2436421 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 2321945 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 114473 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1910914 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 525504 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 93976 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 93966 # Class of control type instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns 187942 # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 20000000 # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 2413067 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntAluAccesses 8696752 # Number of integer alu accesses (Count)
board.processor.cores.core.executeStats0.numIntRegReads 12310923 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 6255421 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 2413067 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 112528 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numMiscRegWrites 392 # Number of times the Misc registers were written (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetchStats0.numInsts 10698812 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 11227639 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.534941 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 2436421 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.121821 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.mmu.alignFaults 0 # Number of MMU faults due to alignment restrictions (Count)
board.processor.cores.core.mmu.prefetchFaults 1 # Number of MMU faults due to prefetch (Count)
board.processor.cores.core.mmu.domainFaults 0 # Number of MMU faults due to domain restrictions (Count)
board.processor.cores.core.mmu.permsFaults 0 # Number of MMU faults due to permissions restrictions (Count)
board.processor.cores.core.mmu.dtb.readHits 1650875 # Read hits (Count)
board.processor.cores.core.mmu.dtb.readMisses 16278 # Read misses (Count)
board.processor.cores.core.mmu.dtb.writeHits 804321 # Write hits (Count)
board.processor.cores.core.mmu.dtb.writeMisses 529 # Write misses (Count)
board.processor.cores.core.mmu.dtb.inserts 16806 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.dtb.flushTlb 16758 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.dtb.flushedEntries 16787 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.dtb.readAccesses 1667153 # Read accesses (Count)
board.processor.cores.core.mmu.dtb.writeAccesses 804850 # Write accesses (Count)
board.processor.cores.core.mmu.dtb.hits 2455196 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.dtb.misses 16807 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.dtb.accesses 2472003 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.dtb_walker.walks 16801 # Table walker walks requested (Count)
board.processor.cores.core.mmu.dtb_walker.walksLongDescriptor 16801 # Table walker walks initiated with long descriptors (Count)
board.processor.cores.core.mmu.dtb_walker.walksLongTerminatedAtLevel::Level2 26 # Level at which table walker walks with long descriptors terminate (Count)
board.processor.cores.core.mmu.dtb_walker.walksLongTerminatedAtLevel::Level3 16775 # Level at which table walker walks with long descriptors terminate (Count)
board.processor.cores.core.mmu.dtb_walker.walkWaitTime::samples 16801 # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkWaitTime::0 16801 100.00% 100.00% # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkWaitTime::total 16801 # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::samples 16801 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::mean 14051.723112 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::gmean 13993.865919 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::stdev 2688.047315 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::0-16383 16783 99.89% 99.89% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::16384-32767 1 0.01% 99.90% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::32768-49151 1 0.01% 99.90% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::49152-65535 11 0.07% 99.97% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::81920-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::163840-180223 1 0.01% 99.99% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.walkServiceTime::total 16801 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.dtb_walker.pendingWalks::samples 105880000 # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.dtb_walker.pendingWalks::0 105880000 100.00% 100.00% # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.dtb_walker.pendingWalks::total 105880000 # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.dtb_walker.pageSizes::4KiB 16775 99.85% 99.85% # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.dtb_walker.pageSizes::2MiB 26 0.15% 100.00% # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.dtb_walker.pageSizes::total 16801 # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::Data 16801 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Requested::total 16801 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::Data 16801 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin_Completed::total 16801 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.requestOrigin::total 33602 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.dtb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.instHits 10696872 # Inst hits (Count)
board.processor.cores.core.mmu.itb.instMisses 37 # Inst misses (Count)
board.processor.cores.core.mmu.itb.inserts 37 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.itb.flushTlb 16758 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.itb.flushedEntries 19 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.itb.instAccesses 10696909 # Inst accesses (Count)
board.processor.cores.core.mmu.itb.hits 10696872 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.itb.misses 37 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.itb.accesses 10696909 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.itb_walker.walks 34 # Table walker walks requested (Count)
board.processor.cores.core.mmu.itb_walker.walksLongDescriptor 34 # Table walker walks initiated with long descriptors (Count)
board.processor.cores.core.mmu.itb_walker.walksLongTerminatedAtLevel::Level2 17 # Level at which table walker walks with long descriptors terminate (Count)
board.processor.cores.core.mmu.itb_walker.walksLongTerminatedAtLevel::Level3 17 # Level at which table walker walks with long descriptors terminate (Count)
board.processor.cores.core.mmu.itb_walker.walkWaitTime::samples 34 # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkWaitTime::0 34 100.00% 100.00% # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkWaitTime::total 34 # Table walker wait (enqueue to first request) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::samples 34 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::mean 43764.705882 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::gmean 15550.898595 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::stdev 60295.765379 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::0-16383 19 55.88% 55.88% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::49152-65535 9 26.47% 82.35% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::65536-81919 1 2.94% 85.29% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::81920-98303 1 2.94% 88.24% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::131072-147455 1 2.94% 91.18% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::180224-196607 2 5.88% 97.06% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::245760-262143 1 2.94% 100.00% # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.walkServiceTime::total 34 # Table walker service (enqueue to completion) latency (Tick)
board.processor.cores.core.mmu.itb_walker.pendingWalks::samples 105525000 # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.itb_walker.pendingWalks::0 105525000 100.00% 100.00% # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.itb_walker.pendingWalks::total 105525000 # Table walker pending requests distribution (Tick)
board.processor.cores.core.mmu.itb_walker.pageSizes::4KiB 17 50.00% 50.00% # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.itb_walker.pageSizes::2MiB 17 50.00% 100.00% # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.itb_walker.pageSizes::total 34 # Table walker page sizes translated (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::Inst 34 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Requested::total 34 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::Inst 34 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin_Completed::total 34 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.requestOrigin::total 68 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.itb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.l2_shared.partialHits 16782 # partial translation hits (Count)
board.processor.cores.core.mmu.l2_shared.instHits 16 # Inst hits (Count)
board.processor.cores.core.mmu.l2_shared.instMisses 21 # Inst misses (Count)
board.processor.cores.core.mmu.l2_shared.readHits 16259 # Read hits (Count)
board.processor.cores.core.mmu.l2_shared.readMisses 19 # Read misses (Count)
board.processor.cores.core.mmu.l2_shared.writeHits 515 # Write hits (Count)
board.processor.cores.core.mmu.l2_shared.writeMisses 14 # Write misses (Count)
board.processor.cores.core.mmu.l2_shared.inserts 16846 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.l2_shared.flushTlb 16758 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.l2_shared.flushedEntries 16802 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.l2_shared.readAccesses 16278 # Read accesses (Count)
board.processor.cores.core.mmu.l2_shared.writeAccesses 529 # Write accesses (Count)
board.processor.cores.core.mmu.l2_shared.instAccesses 37 # Inst accesses (Count)
board.processor.cores.core.mmu.l2_shared.hits 16790 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.l2_shared.misses 54 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.l2_shared.accesses 16844 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.readHits 0 # Read hits (Count)
board.processor.cores.core.mmu.stage2_dtb.readMisses 0 # Read misses (Count)
board.processor.cores.core.mmu.stage2_dtb.writeHits 0 # Write hits (Count)
board.processor.cores.core.mmu.stage2_dtb.writeMisses 0 # Write misses (Count)
board.processor.cores.core.mmu.stage2_dtb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.stage2_dtb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.stage2_dtb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.stage2_dtb.readAccesses 0 # Read accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.writeAccesses 0 # Write accesses (Count)
board.processor.cores.core.mmu.stage2_dtb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.stage2_dtb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.stage2_dtb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_dtb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.stage2_itb.instHits 0 # Inst hits (Count)
board.processor.cores.core.mmu.stage2_itb.instMisses 0 # Inst misses (Count)
board.processor.cores.core.mmu.stage2_itb.inserts 0 # Number of times an entry is inserted into the TLB (Count)
board.processor.cores.core.mmu.stage2_itb.flushTlb 0 # Number of times a TLB invalidation was requested (Count)
board.processor.cores.core.mmu.stage2_itb.flushedEntries 0 # Number of entries that have been flushed from TLB (Count)
board.processor.cores.core.mmu.stage2_itb.instAccesses 0 # Inst accesses (Count)
board.processor.cores.core.mmu.stage2_itb.hits 0 # Total TLB (inst and data) hits (Count)
board.processor.cores.core.mmu.stage2_itb.misses 0 # Total TLB (inst and data) misses (Count)
board.processor.cores.core.mmu.stage2_itb.accesses 0 # Total TLB (inst and data) accesses (Count)
board.processor.cores.core.mmu.stage2_itb_walker.walks 0 # Table walker walks requested (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst (Count)
board.processor.cores.core.mmu.stage2_itb_walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.realview.bootmem.bytesRead::processor.cores.core.inst 336 # Number of bytes read from this memory (Byte)
board.realview.bootmem.bytesRead::processor.cores.core.data 68 # Number of bytes read from this memory (Byte)
board.realview.bootmem.bytesRead::total 404 # Number of bytes read from this memory (Byte)
board.realview.bootmem.bytesInstRead::processor.cores.core.inst 336 # Number of instructions bytes read from this memory (Byte)
board.realview.bootmem.bytesInstRead::total 336 # Number of instructions bytes read from this memory (Byte)
board.realview.bootmem.numReads::processor.cores.core.inst 84 # Number of read requests responded to by this memory (Count)
board.realview.bootmem.numReads::processor.cores.core.data 9 # Number of read requests responded to by this memory (Count)
board.realview.bootmem.numReads::total 93 # Number of read requests responded to by this memory (Count)
board.realview.bootmem.bwRead::processor.cores.core.inst 16800 # Total read bandwidth from this memory ((Byte/Second))
board.realview.bootmem.bwRead::processor.cores.core.data 3400 # Total read bandwidth from this memory ((Byte/Second))
board.realview.bootmem.bwRead::total 20200 # Total read bandwidth from this memory ((Byte/Second))
board.realview.bootmem.bwInstRead::processor.cores.core.inst 16800 # Instruction read bandwidth from this memory ((Byte/Second))
board.realview.bootmem.bwInstRead::total 16800 # Instruction read bandwidth from this memory ((Byte/Second))
board.realview.bootmem.bwTotal::processor.cores.core.inst 16800 # Total bandwidth to/from this memory ((Byte/Second))
board.realview.bootmem.bwTotal::processor.cores.core.data 3400 # Total bandwidth to/from this memory ((Byte/Second))
board.realview.bootmem.bwTotal::total 20200 # Total bandwidth to/from this memory ((Byte/Second))
board.realview.bootmem.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.clcd.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.clock24MHz.clock 41667 # Clock period in ticks (Tick)
board.realview.clock32KHz.clock 31250000 # Clock period in ticks (Tick)
board.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks (Tick)
board.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks (Tick)
board.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks (Tick)
board.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks (Tick)
board.realview.dcc.osc_smb.clock 20000 # Clock period in ticks (Tick)
board.realview.dcc.osc_sys.clock 16667 # Clock period in ticks (Tick)
board.realview.el2_watchdog.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.energy_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.flash0.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.flash1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.generic_timer_mem.frames0.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.generic_timer_mem.frames1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.generic_timer_mem.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.gic.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.io_voltage.voltage 3.300000 # Voltage in Volts (Volt)
board.realview.kmi0.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.kmi1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks (Tick)
board.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks (Tick)
board.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks (Tick)
board.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks (Tick)
board.realview.non_trusted_sram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.pwr_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.realview_io.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.rtc.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.sp810_fake.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.system_watchdog.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.trusted_dram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.trusted_sram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.trusted_watchdog.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.uart0.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.uart1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.uart2.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.uart3.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.vio0.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.vio1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.vram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.realview.watchdog.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------